7477 datasheet(13/354 Pages) RENESAS

13 / 354 page

List of figures

7470/7471/7477/7478 GROUP USER’S MANUAL

Fig. 1.11.11 Structure of Interrupt control register 1 ............................................................... 1-61

Fig. 1.11.12 Structure of Interrupt control register 2 ............................................................... 1-61

Fig. 1.12.1 Timer block diagram .................................................................................................. 1-63

Fig. 1.12.2 Timer count timing ..................................................................................................... 1-64

Fig. 1.12.3 Example of timer mode operation ........................................................................... 1-66

Fig. 1.12.4 Example of event counter mode operation ........................................................... 1-70

Fig. 1.12.5 Example of pulse output mode operation .............................................................. 1-72

Fig. 1.12.6 Example of operation of external pulse width measurement mode................... 1-75

Fig. 1.12.7 Example of operation of PWM output mode ......................................................... 1-78

Fig. 1.12.8 Example of updating of Timer 1, Timer 2 and Timer latch ................................ 1-80

Fig. 1.12.9 Example of updating of Timer 3, Timer 4 and Timer latch in PWM mode ...... 1-81

Fig. 1.12.10 Relation between timer value change timing and read value change timing 1-82

Fig. 1.12.11 Structure of Timers 1 to 4 ......................................................................................1-83

Fig. 1.12.12 Structure of Timer 12 mode register .................................................................... 1-84

Fig. 1.12.13 Structure of Timer 34 mode register .................................................................... 1-85

Fig. 1.12.14 Structure of Timer mode register 2 ...................................................................... 1-86

Fig. 1.12.15 Structure of Timer FF register .............................................................................. 1-86

Fig. 1.12.16 Structure of Input latch register ............................................................................ 1-87

Fig. 1.12.17 Sturucture of Edge polarity selection register..................................................... 1-88

Fig. 1.13A.1 Serial I/O block diagram ......................................................................................... 1-90

Fig. 1.13A.2 Serial I/O transmit operation .................................................................................. 1-93

Fig. 1.13A.3 Serial I/O transmit timing chart ............................................................................. 1-93

Fig. 1.13A.4 Serial I/O receive operation ...................................................................................1-96

Fig. 1.13A.5 Serial I/O receive timing chart .............................................................................. 1-96

Fig. 1.13A.6 Transmit/receive operation in byte specification mode ..................................... 1-99

Fig. 1.13A.7 Structure of Serial I/O register ........................................................................... 1-102

Fig. 1.13A.8 Structure of Serial I/O counter and Byte counter ............................................ 1-103

Fig. 1.13A.9 Structure of Serial I/O mode register ................................................................ 1-104

Fig. 1.13B.1 Clock synchronous serial I/O block diagram .................................................... 1-105

Fig. 1.13B.2 Transmit operation of clock synchronous serial I/O ........................................ 1-108

Fig. 1.13B.3 Transmit timing chart of clock synchronous serial I/O .................................... 1-109

Fig. 1.13B.4 Receive operation of clock synchronous serial I/O ......................................... 1-112

Fig. 1.13B.5 Receive timing chart of clock synchronous serial I/O ..................................... 1-112

Fig. 1.13B.6 UART block diagram ............................................................................................ 1-114

Fig. 1.13B.7 UART data format.................................................................................................. 1-117

Fig. 1.13B.8 Transmit/receive format of UART ....................................................................... 1-118

Fig. 1.13B.9 Transmit operation of UART ............................................................................... 1-120

Fig. 1.13B.10 Transmit timing chart of UART ......................................................................... 1-121

Fig. 1.13B.11 Receive operation of UART .............................................................................. 1-124

Fig. 1.13B.12 Receive timing chart of UART .......................................................................... 1-125

Fig. 1.13B.13 Structure of Transmit/receive buffer register .................................................. 1-131

Fig. 1.13B.14 Structure of Serial I/O status register ............................................................. 1-132

Fig. 1.13B.15 Structure of Serial I/O control register ............................................................ 1-135

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