7477 datasheet(86/354 Pages) RENESAS

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7470/7471/7477/7478 GROUP USER’S MANUAL

HARDWARE

1.12 Timers

(2) Event counter mode

In the event counter mode, the same operations as those in the timer mode are performed, with the

exception that the signal input from the CNTR0 pin becomes a count source of Timer 1 and the signal

input from the CNTR1 pin becomes a count source of Timer 3 and Timer 4.

The operation in the event counter mode are described below.

1 Start of count operation

After the count stop bit is cleared to “0,” a count operation starts. Each time a count source is

input, the contents of the timer are decremented by 1.

For the active edge of count source, a rise or a fall can be selected by the edge polarity selection

Note: Because the count stop bit is “0” immediately after reset release, the count operation is

automatically started after reset release but the count source is not a CNTR pin input (operates

as the timer mode).

2 Reload operation

When the timer overflows, the value resulting from decrementing 1 from the contents of the timer

latch is transferred (reloaded) to the timer.

3 Interrupt operation

2Timer interrupt

When the timer overflows, an interrupt request occurs, so that the interrupt request bit is set

to “1.” The acceptance of interrupt is controlled by the interrupt enable bit of each timer.

2CNTR interrupt

An interrupt request is generated from the edge of the count source input from the CNTR0 pin

or the CNTR1 pin, so that the interrupt request is set to “1.” The acceptance of interrupt is

controlled by the interrupt enable bit of each timer.

The edge polarity selection register selects an active edge of count source and a CNTR0/

CNTR1 interrupt.

4 Stop of count operation

When the counter stop bit is set to “1” by software, the count operation stops. (The count operation

continues until “1” is set in the count stop bit.)

Figure 1.12.4 shows an example of event counter mode operation.

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