7477 datasheet(68/354 Pages) RENESAS

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7470/7471/7477/7478 GROUP USER’S MANUAL

HARDWARE

1.11 Interrupts

1-51

(3) CNTR interrupt

When detecting a rising edge or a falling edge of each CNTR pin (CNTR0, CNTR1), the microcomputer

generates an CNTR interrupt. For selecting the active edge of interrupt and the CNTR0/CNTR1 pin,

the Edge polarity selection register (EG) is used.

2 After reset

At reset release, the Edge polarity selection register is cleared to “0016,” so the CNTR0 interrupts

generate the interrupt request by detecting a falling edge. At reset release, however, the Interrupt

control register is put into the interrupt disable state, so any interrupt is not accepted.

Note: The CNTR0 and CNTR1 pins are used in common with input port P32 and P33, however there

is no register for switching between the CNTR pins and the ports, so the active edges of P32

and P33 are always detected. When these pins are used as ports, put the corresponding CNTR

interrupt into the disable state. In the CNTR interrupt enable state, the CNTR interrupt is

generated by a pin level change, thereby causing a program run away.

(4) Timer interrupt

The microcomputer generates the interrupt request at the rise of the next count source after the

respective timer overflows.

For the details of the timer interrupt, refer to “1.12 Timers.”

(5) Serial I/O interrupt

There is a difference in the serial I/O interrupt between the 7470/7471 group and the 7477/7478

group.

2 Serial I/O interrupt of 7470/7471 group

An interrupt request is generated upon termination of the serial I/O transmit/receive.

2 Serial I/O interrupt of 7477/7478 group

The serial I/O transmit interrupt and the serial I/O receive interrupt are available.

q Serial I/O transmit interrupt

For the Serial I/O transmit interrupt, interrupt request generation timing can be selected by bit 3

of the Serial I/O control register (SIOCON: Address 00E216) as shown below.

0: The data written in the Transmit buffer is transferred to the Transmit shift register, and when

the Transmit buffer becomes empty, the interrupt request is generated.

1: The interrupt request is generated when a shift operation of the Transmit shift register terminates.

Note: When the transmit enable bit is set to the enable state, the Transmit buffer becomes empty

and the transmit shift terminates. Accordingly, the interrupt request can be generated by

selecting one of these sources. To use the transmit interrupt, set the transmit enable bit to “1,”

clear the transmit interrupt request bit to “0,” and then set the transmit interrupt enable bit to

the enable state.

q Serial I/O receive interrupt

When all data has been put in the Receive shift register and the contents of the shift register have

been transferred to the Receive buffer, the interrupt request is generated.

For the details of the serial I/O interrupt, refer to “1.13 Serial I/O.”

(6) A-D conversion completion interrupt

As soon as A-D conversion terminates, the interrupt request is generated.

For the details of the A-D conversion completion interrupt, refer to “1.14 A-D Converter.”

(7) BRK instruction interrupt

This is the lowest-priority software interrupt without any corresponding interrupt enable flag, and not

affected by the interrupt disable flag. (Non maskable)

For the details, refer to “SERIES 740 SOFTWARE USER’S MANUAL.”

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