7477 datasheet(14/354 Pages) RENESAS

14 / 354 page

7470/7471/7477/7478 GROUP USER’S MANUAL

List of figures

iii

Fig. 1.13B.16 Structure of UART control register .................................................................. 1-138

Fig. 1.14.1 A-D converter block diagram ................................................................................. 1-139

Fig. 1.14.2 Contents of A-D conversion register and reference voltage during

A-D conversion ......................................................................................................... 1-141

Fig. 1.14.3 Definition of A-D conversion precision ................................................................. 1-146

Fig. 1.14.4 Structure of A-D conversion register .................................................................... 1-147

Fig. 1.14.5 Structure of A-D control register ........................................................................... 1-148

Fig. 1.15.1 Internal processing sequence after reset release .............................................. 1-149

Fig. 1.15.2 Internal status immediately after reset release ................................................... 1-151

Fig. 1.16.1 Clock generating circuit block diagram ................................................................ 1-153

Fig. 1.16.2 Oscillation stabilizing wait time after power on .................................................. 1-158

Fig. 1.17.1 Operation states of the microcomputer at low-power dissipation .................... 1-160

Fig. 1.17.2 State transition at low-power dissipation ............................................................. 1-161

Fig. 1.17.3 Oscillation stabilizing wait time at recovery from stop mode by reset input . 1-163

Fig. 1.17.4 Example of recovery sequence from stop mode by INT0 interrupt ................. 1-165

Fig. 1.17.5 Reset input time ....................................................................................................... 1-167

Fig. 1.17.6 Structure of CPU mode register ........................................................................... 1-170

Fig. 1.18.1 State transitions ........................................................................................................ 1-172

Fig. 1.19.1 Pin connection in EPROM mode of 7470 group ................................................ 1-176

Fig. 1.19.2 Pin connection in EPROM mode of 7471 group (1) .......................................... 1-177

Fig. 1.19.3 Pin connection in EPROM mode of 7471 group (2) .......................................... 1-178

Fig. 1.19.4 Pin connection in EPROM mode of 7477 group ................................................ 1-179

Fig. 1.19.5 Pin connection in EPROM mode of 7478 group (1) .......................................... 1-180

Fig. 1.19.6 Pin connection in EPROM mode of 7478 group (2) .......................................... 1-181

Fig. 1.19.7 Programming and testing of One Time PROM version ..................................... 1-187

Fig. 1.20.1 Timing chart (7470/7471 group) ............................................................................ 1-200

Fig. 1.20.2 Timing chart (7477/7478 group) ............................................................................ 1-201

Fig. 1.20.3 Power source current standard characteristics measuring circuit .................... 1-202

Fig. 1.20.4 ICC-VCC characteristics (f(XIN) = 8 MHz, 7470/7471 group) ............................. 1-203

Fig. 1.20.5 ICC-VCC characteristics (f(XIN) = 4 MHz, 7470/7471 group) ............................. 1-203

Fig. 1.20.6 ICC-VCC characteristics (f(XCIN) = 32 kHz, 7470/7471 group) .......................... 1-204

Fig. 1.20.7 ICC-VCC characteristics (f(XIN) = 8 MHz, 7477/7478 group) ............................. 1-205

Fig. 1.20.8 ICC-VCC characteristics (f(XIN) = 4 MHz, 7477/7478 group) ............................. 1-205

Fig. 1.20.9 ICC-VCC characteristics (f(XCIN) = 32 kHz, 7477/7478 group) .......................... 1-206

Fig. 1.20.10 Port standard characteristic measuring circuits ................................................ 1-207

Fig. 1.20.11 IOH-VOH characteristics of programmable I/O port (CMOS output) P-channel

side (7470/7471 group) ......................................................................................... 1-208

Fig. 1.20.12 IOL-VOL characteristics of programmable I/O port (CMOS output) N-channel

side (7470/7471 group) ......................................................................................... 1-208

Fig. 1.20.13 IIL-VIL characteristics of programmable I/O port (CMOS output) pull-up

transistor (7470/7471 group) ................................................................................ 1-209

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