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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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7721 датащи(PDF) 246 Page - Renesas Technology Corp |
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7721 датащи(HTML) 246 Page - Renesas Technology Corp |
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246 / 577 page  7721 Group User’s Manual 11–43 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode Fig. 11.4.10 Processing after receive completion [When not using interrupts] [When using interrupts] A UARTi receive interrupt request occurs when reception is completed. UARTi receive interrupt Processing after reading out receive data UART0 receive buffer register (Addresses 3716, 3616) UART1 receive buffer register (Addresses 3F16, 3E16) b15 b8 Reading of receive data Read out receive data. b7 b0 0 0 0 0 0 0 0 UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 Receive complete flag 0 : Reception not completed 1 : Reception completed Checking completion of reception 1 UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 Checking error Framing error flag Parity error flag Error sum flag 0 : No error 1 : Error detected 1 Note : This figure shows the bits and registers required for processing. Refer to “Figure 11.4.12” for the change of flag state and the occurrence timing of an interrupt request. UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 Checking error Overrun error flag 0 : No overrun error 1 : Overrun error detected 1 |
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