SH7021 datasheet(32/509 Pages) RENESAS

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RENESAS 11

Table 1.3

Pin Functions (cont)

Type

Symbol

Pin No.

I/O

Name and Function

Bus

control

RAS

Row address strobe: DRAM row-address strobe-timing

signal.

(cont)

CASH

Column address strobe high: DRAM column-address

strobe-timing signal outputs low level to access the

upper eight data bits.

CASL

Column address strobe low: DRAM column-address

strobe-timing signal outputs low level to access the

lower eight data bits.

Read: Indicates reading of data from an external device.

WRH

Upper write: Indicates write access to the upper eight

bits of an external device.

WRL

Lower write: Indicates write access to the lower eight

bits of an external device.

CS0–CS7

46–49,

51–54

Chip select 0–7: Chip select signals for accessing

external memory and devices.

Address hold: Address hold timing signal for a device

using a multiplexed address/data bus.

HBS, LBS

20, 56

Upper/lower byte strobe: Upper and lower byte strobe

signals. (Also used as WRH and A0.)

Write: Brought low during write access. (Also used as

WRL.)

DMAC

DREQ0,

DREQ1

66, 68

DMA transfer request (channels 0 and 1): Input pins for

external DMA transfer requests.

DACK0,

DACK1

65, 67

DMA transfer acknowledge (channels 0 and 1):

Indicates that DMA transfer is acknowledged.

16-bit

integrated-

TIOCA0,

TIOCB0

51, 53

I/O

ITU input capture/output compare (channel 0): Input

capture or output compare pins.

timer pulse

unit (ITU)

TIOCA1,

TIOCB1

62, 64

I/O

ITU input capture/output compare (channel 1): Input

capture or output compare pins.

TIOCA2,

TIOCB2

83, 84

I/O

ITU input capture/output compare (channel 2): Input

capture or output compare pins.

TIOCA3,

TIOCB3

85, 86

I/O

ITU input capture/output compare (channel 3): Input

capture or output compare pins.

TIOCA4,

TIOCB4

87, 89

I/O

ITU input capture/output compare (channel 4): Input

capture or output compare pins.

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