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SH7021 датащи(PDF) 98 Page - Renesas Technology Corp

номер детали SH7021
подробное описание детали  SuperH??RISC engine
PDF  509 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7021 датащи(HTML) 98 Page - Renesas Technology Corp

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RENESAS 79
BAMRL: Break address mask register L.
Bit:
15
14
13
12
11
10
9
8
Bit name:
BAM15
BAM14
BAM13
BAM12
BAM11
BAM10
BAM9
BAM8
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Bit name:
BAM7
BAM6
BAM5
BAM4
BAM3
BAM2
BAM1
BAM0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
•
BAMRL bits 15–0 (break address mask 15–0 (BAM15–BAM0)): BAM15–BAM0 specify
whether bits BA15–BA0 of the break address set in BARH are masked or not.
Bits 15–0: BAMn
Description
0
Break address bit BAn is included in the break condition (initial value)
1
Break address bit BAn is not included in the break condition
n = 31–0
6.2.3
Break Bus Cycle Register (BBR)
The break bus cycle register (BBR) is a 16-bit read/write register that selects the following four
break conditions:
•
CPU cycle or DMA cycle
•
Instruction fetch or data access
•
Read or write
•
Operand size (byte, word, long word).
A reset initializes BBR to H'0000. It is not initialized in the standby mode.



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