SH7021 datasheet(13/509 Pages) RENESAS

13 / 509 page

5.3.2

Interrupt Control Register (ICR) ..........................................................................

5.4

Interrupt Operation ............................................................................................................

5.4.1

Interrupt Sequence................................................................................................

5.4.2

Stack after Interrupt Exception Processing ..........................................................

5.5

Interrupt Response Time....................................................................................................

5.5

Usage Notes .......................................................................................................................

Section 6 User Break Controller (UBC) ...................................................................... 75

6.1

Overview............................................................................................................................

6.1.1

Features ................................................................................................................

6.1.2

Block Diagram......................................................................................................

6.1.3

6.2

Register Descriptions.........................................................................................................

6.2.1

Break Address Registers (BAR) ..........................................................................

6.2.2

Break Address Mask Register (BAMR)...............................................................

6.2.3

Break Bus Cycle Register (BBR) .........................................................................

6.3

Operation ...........................................................................................................................

6.3.1

Flow of the User Break Operation........................................................................

6.3.2

Break on Instruction Fetch Cycles to On-Chip Memory......................................

6.3.3

Program Counter (PC) Value Saved in User Break Interrupt Exception

Processing.............................................................................................................

6.4

Setting User Break Conditions ..........................................................................................

6.5

Notes..................................................................................................................................

6.5.1

On-Chip Memory Instruction Fetch .....................................................................

6.5.2

Instruction Fetch at Branches ...............................................................................

6.5.3

Instruction Fetch Break ........................................................................................

Section 7 Clock Pulse Generator (CPG) ..................................................................... 89

7.1

Overview............................................................................................................................

7.2

Clock Source......................................................................................................................

7.2.1

Connecting a Crystal Resonator ...........................................................................

7.2.2

External Clock Input ............................................................................................

7.3

Usage Notes .......................................................................................................................

Section 8 Bus State Controller (BSC) ........................................................................... 93

8.1

Overview............................................................................................................................

8.1.1

Features ................................................................................................................

8.1.2

Block Diagram......................................................................................................

8.1.3

Pin Configuration .................................................................................................

8.1.4

8.1.5

Overview of Areas................................................................................................

8.2

Register Descriptions.........................................................................................................

8.2.1

Bus Control Register (BCR) ................................................................................

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