SH7021 datasheet(12/509 Pages) RENESAS

12 / 509 page

4.1.1

Exception Processing Types and Priorities ..........................................................

4.1.2

Exception Processing Operation ..........................................................................

4.1.3

Exception Process Vector Table ..........................................................................

4.2

Reset ..................................................................................................................................

4.2.1

Reset Types ..........................................................................................................

4.2.2

Power-On Reset....................................................................................................

4.2.3

Manual Reset........................................................................................................

4.3

Address Errors ...................................................................................................................

4.3.1

Address Error Sources..........................................................................................

4.3.2

Address Error Exception Processing....................................................................

4.4

Interrupts............................................................................................................................

4.4.1

Interrupt Sources ..................................................................................................

4.4.2

Interrupt Priority Rankings...................................................................................

4.4.3

Interrupt Exception Processing ............................................................................

4.5

Instruction Exceptions .......................................................................................................55

4.5.1

Types of Instruction Exceptions ...........................................................................

4.5.2

Trap Instruction ....................................................................................................

4.5.3

Illegal Slot Instruction ..........................................................................................

4.5.4

General Illegal Instructions ..................................................................................

4.6

Cases in Which Exceptions Are Not Accepted .................................................................

4.6.1

Immediately after Delayed Branch Instructions...................................................

4.6.2

Immediately after Interrupt-Disabling Instructions..............................................

4.7

Stack Status after Exception Processing............................................................................

4.8

Notes..................................................................................................................................

4.8.1

Value of the Stack Pointer (SP)............................................................................

4.8.2

Value of the Vector Base Register (VBR) ...........................................................

4.8.3

Address Errors that Are Caused by Stacking During Address Error

Exception Processing............................................................................................

Section 5 Interrupt Controller (INTC) .......................................................................... 61

5.1

Overview............................................................................................................................

5.1.1

Features ................................................................................................................

5.1.2

Block Diagram......................................................................................................

5.1.3

Pin Configuration .................................................................................................

5.1.4

Registers ...............................................................................................................

5.2

Interrupt Sources................................................................................................................

5.2.1

NMI Interrupts......................................................................................................

5.2.2

User Break Interrupt .............................................................................................

5.2.3

IRQ Interrupts ......................................................................................................

5.2.4

On-Chip Interrupts................................................................................................

5.2.5

Interrupt Exception Vectors and Priority Rankings .............................................

5.3

Register Descriptions.........................................................................................................

5.3.1

Interrupt Priority Registers A–E (IPRA–IPRE) ...................................................

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