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SH7021 датащи(PDF) 73 Page - Renesas Technology Corp |
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SH7021 датащи(HTML) 73 Page - Renesas Technology Corp |
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73 / 509 page ![]() RENESAS 53 Table 4.5 Address Error Sources Bus Cycle Type Bus Master Operation Address Error Instruction fetch CPU Instruction fetch from even address None (normal) Instruction fetch from odd address Address error Instruction fetch from outside on-chip peripheral module space None (normal) Instruction fetch from on-chip peripheral module space Address error Data read/write CPU or DMAC Access to word data from even address None (normal) Access to word data from odd address Address error Access to long word data aligned on long word boundary None (normal) Access to long word data not aligned on long word boundary Address error Access to word or byte data in on-chip peripheral module space* None (normal) Access to long word data in 16-bit on-chip peripheral module space* None (normal) Access to long word data in 8-bit on-chip peripheral module space* Address error Note: See section 8, Bus State Controller, for details on the on-chip peripheral module space. 4.3.2 Address Error Exception Processing When an address error occurs, address error exception processing starts after both the bus cycle that caused the address error and the instructions that were being executed at that time have been completed. The CPU then: 1. Pushes the SR onto the stack. 2. Pushes the program counter onto the stack. The PC value saved is the top address of the instruction following the last instruction to be executed. 3. Fetches the exception service routine start address from the exception vector table for the address error that occurred and starts program execution from that address. The branch that occurs here is not a delayed branch. |
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