32186 datasheet(25/1032 Pages) RENESAS

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OVERVIEW

1-7

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

1.2 Block Diagram

Table 1.2.1 Features of the 32185/32186 (2/3)

Functional Block

Features

A/D Converter (ADC)

• 16 channels: 10-bit resolution A/D converter × 1 block

• Conversion modes: In addition to ordinary A/D conversion modes, the ADC incorporates

comparator mode and 2-channel simultaneous sampling mode.

• Operation modes: Single conversion mode and n-channel scan mode (n = 1–16)

• A/D conversion with the analog input voltages sampled at start of A/D conversion is performable

byusing sample-and-hold function.

• Effects of the analog input voltage leakage from the preceding channel during A/D conversion is

deterrable by using A/D disconnection detection assist function.

• An inflow current bypass circuit is built-in.

• Can generate an interrupt or start DMA transfer upon completion of A/D conversion.

• Either 8 or 10-bit conversion results can be read out.

• Interrupt request: Completion of A/D conversion

• DMA transfer request: Completion of A/D conversion

Serial Interface (SIO)

• 6-channel serial interface

• Can be chosen to be clock-synchronous serial interface or clock-asynchronous serial interface.

• Data can be transferred at high speed (2.5 Mbits per second during clock-synchronous mode or

1.25 Mbits per second during clock-asynchronous mode when f(BCLK) = 20 MHz).

• Interrupt request: Reception completed, receive error, transmit buffer empty or transmission completed

• DMA transfer request: Reception completed or transmit buffer empty

CAN

• 32 message slots × 2 blocks

• Compliant with CAN specification 2.0B active.

• Interrupt request: Transmission completed, reception completed, bus error, error-passive, bus-off

or single shot

• DMA transfer request: Failed to send, transmission completed or reception completed

Real-Time Debugger

• Internal RAM can be rewritten or monitored independently of the CPU by entering a command

(RTD)

from the outside.

• Comes with exclusive clock-synchronous serial ports.

• Interrupt request: RTD interrupt command input

Non-Break Debug

• Can access to all resources on the address map from the outside

(NBD)

• Clock-synchronous parallel interface (4-bit)

• Event output function

• RAM monitor function

Direct RAM Interface

• Can control capture of clock-synchronous parallel data to the internal RAM independently of the CPU

(DRI)

• Clock-synchronous parallel input (8, 16 or 32-bit)

• Maximum transfer rate: 20 Mbytes/s (when f(CPUCLK)=80 MHz)

Interrupt Controller (ICU)

• Controls interrupt requests from the internal peripheral I/O.

• Supports 8-level interrupt priority including an interrupt disabled state.

• External interrupt: 27 sources (SBI#, TIN0, TIN3–TIN11, TIN16–TIN27, TIN30–TIN33)

• TIN pin input sensing: Rising, falling or both edges or “H” or “L” level

Wait Controller

• Controls wait states for access to the external extension area.

• Insertion of 0–15 wait states by setting up in software + wait state extension by entering WAIT# signal

PLL

• A multiply-by-8 clock generating circuit

Clock

• The Maximum external input clock frequency (XIN) is 10.0 MHz.

• CPUCLK: Operating clock for the M32R-FPU core, internal flash memory and internal RAM

The Maximum CPU clock is 80 MHz (when f(XIN) = 10 MHz).

• BCLK: Operating clock for the peripheral I/O and external data bus

The Maximum peripheral clock is 20 MHz (peripheral module access when f(XIN) = 10 MHz).

• BCLK pin output: A clock with the same frequency as f(BCLK) is output from this pin.

• CLKOUT pin output: A clock with the same or half frequency as f(BCLK) is output from this pin.

JTAG

• Boundary scan function

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