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32186 датащи(PDF) 23 Page - Renesas Technology Corp |
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32186 датащи(HTML) 23 Page - Renesas Technology Corp |
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23 / 1032 page ![]() 1 OVERVIEW 1-5 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 1.2 Block Diagram 1.2 Block Diagram Figure 1.2.1 shows a block diagram of the 32185/32186. The features of each block are described in Table 1.2.1. Figure 1.2.1 Block Diagram of the 32185/32186 M32R-FPU Core (Max. 80MHz) Non-Break Debug (NBD) Direct RAM Interface (DRI) Multiplier/Accumulator (32 bits x 16 bits + 56 bits) Single-precision FPU (fully IEEE 754 compliant) Internal Flash Memory (M32185F4: 512 Kbytes) (M32186F8: 1 Mbyte) Internal RAM (M32185F4: 32 Kbytes) (M32186F8: 64 Kbytes) PLL Clock Generator Internal Power Supply Generator (VDC) Address Data External Bus Interface Input/output ports, 97 lines Real-Time Debugger (RTD) Internal Bus Interface DMAC (10 channels) Multijunction Timer (MJT: 55 channels) A/D Converter (A/D0 : 10-bit converter, 16 channels) Serial Interface (6 channels) Interrupt Controller (8 levels) Wait Controller Full CAN (2 channels) |
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