32186 datasheet(6/1032 Pages) RENESAS

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Contents-1

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Table of Contents

CHAPTER 1 OVERVIEW

1.1 Outline of 32185/32186 Group ........................................................................................................... 1-2

1.1.1 M32R Family CPU Core with Built-in FPU (M32R-FPU) ............................................................ 1-2

1.1.2 Built-in Multiplier/Accumulator .................................................................................................... 1-3

1.1.3 Built-in Single-precision FPU ...................................................................................................... 1-3

1.1.4 Built-in Flash Memory and RAM ................................................................................................. 1-3

1.1.5 Built-in Clock Frequency Multiplier ............................................................................................. 1-4

1.1.6 Powerful Peripheral Functions Built-in ....................................................................................... 1-4

1.2 Block Diagram .................................................................................................................................... 1-5

1.3 Pin Functions ..................................................................................................................................... 1-9

1.4 Pin Assignments ................................................................................................................................. 1-13

CHAPTER 2 CPU

2.1 CPU Registers ................................................................................................................................... 2-2

2.2 General-purpose Registers ................................................................................................................ 2-2

2.3 Control Registers ............................................................................................................................... 2-2

2.3.1 Processor Status Word Register: PSW (CR0) ............................................................................ 2-3

2.3.2 Condition Bit Register: CBR (CR1) ............................................................................................ 2-4

2.3.3 Interrupt Stack Pointer: SPI (CR2) and User Stack Pointer: SPU (CR3) .................................... 2-4

2.3.4 Backup PC: BPC (CR6) ............................................................................................................. 2-4

2.3.5 Floating-point Status Register: FPSR (CR7) .............................................................................. 2-5

2.4 Accumulator ....................................................................................................................................... 2-7

2.5 Program Counter ................................................................................................................................ 2-7

2.6 Data Formats ...................................................................................................................................... 2-8

2.6.1 Data Types ................................................................................................................................. 2-8

2.6.2 Data Formats ............................................................................................................................. 2-9

2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution ................ 2-14

CHAPTER 3 ADDRESS SPACE

3.1 Outline of Address Space ................................................................................................................... 3-2

3.2 Operation Modes ................................................................................................................................ 3-3

3.3 Internal ROM and External Extension Areas ...................................................................................... 3-6

3.3.1 Internal ROM Area ..................................................................................................................... 3-6

3.3.2 External Extension Area ............................................................................................................. 3-6

3.4 Internal RAM and SFR Areas ............................................................................................................. 3-7

3.4.1 Internal RAM Area ...................................................................................................................... 3-7

3.4.2 SFR (Special Function Register) Area ........................................................................................ 3-7

3.5 EIT Vector Entry ................................................................................................................................. 3-47

3.6 ICU Vector Table ................................................................................................................................ 3-48

3.7 Notes on Address Space .................................................................................................................... 3-51

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