32186 datasheet(22/1032 Pages) RENESAS

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OVERVIEW

1-4

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

1.1 Outline of 32185/32186 Group

1.1.5 Built-in Clock Frequency Multiplier

• The 32185/32186 contains a clock frequency multiplier, which is schematically shown in Figure 1.1.1

below.

1/4

PLL

1/2

CLKO

SEL

CLKOUT(external bus clock)

(20MHz or 10MHz)

XIN pin

(10MHz)

BCLK (peripheral clock)

(20MHz)

CPUCLK (CPU clock)

(80MHz)

Figure 1.1.1 Conceptual Diagram of the Clock Frequency Multiplier

Table 1.1.2 Clock

Functional Block

Features

CPUCLK

• CPU clock: Defined as f(CPUCLK) when it indicates the operating clock frequency for

the M32R-FPU core, internal flash memory and internal RAM.

BCLK

• Peripheral clock: Defined as f(BCLK) when it indicates the operating clock frequency

for the internal peripheral I/O and external data bus.

Clock output

• BCLK pin output: A clock with the same frequency as f(BCLK) is output from this pin.

• CLKOUT pin output: A clock with the same or half frequency as f(BCLK) is output from this pin.

1.1.6 Powerful Peripheral Functions Built-in

(1) 8-level interrupt controller (ICU)

(2) 10-channel DMAC

(3) 55-channel multijunction timer (MJT)

(4) 16-channel A/D converter (ADC)

(5) 6-channel serial interface (SIO)

(6) 2-channel Full-CAN

(7) Direct RAM interface (DRI)

(8) Real-time debugger (RTD)

(9) Non-break debug (NBD)

(10) Wait controller

(11) M32R Family’s common debug function (Scalable Debug Interface or SDI)

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