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HD6432351 датащи(PDF) 308 Page - Renesas Technology Corp |
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HD6432351 датащи(HTML) 308 Page - Renesas Technology Corp |
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308 / 1025 page ![]() Section 7 DMA Controller (DMAC) Rev. 3.00 Sep 15, 2006 page 274 of 988 REJ09B0330-0300 Single Address Mode (Write) Figure 7.29 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write φ Address bus DMA dead HWR DACK TEND Bus release LWR DMA write DMA write DMA write Bus release Bus release Bus release Bus release Last transfer cycle Figure 7.29 Example of Single Address Mode (Byte Write) Transfer |
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