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HD6432351 датащи(PDF) 306 Page - Renesas Technology Corp |
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HD6432351 датащи(HTML) 306 Page - Renesas Technology Corp |
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306 / 1025 page ![]() Section 7 DMA Controller (DMAC) Rev. 3.00 Sep 15, 2006 page 272 of 988 REJ09B0330-0300 7.5.11 DMAC Bus Cycles (Single Address Mode) Single Address Mode (Read) Figure 7.27 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read φ Address bus DMA dead RD DACK TEND Bus release DMA read DMA read DMA read Bus release Bus release Bus release Bus release Last transfer cycle Figure 7.27 Example of Single Address Mode (Byte Read) Transfer |
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