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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HD6432351 датащи(PDF) 253 Page - Renesas Technology Corp |
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HD6432351 датащи(HTML) 253 Page - Renesas Technology Corp |
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253 / 1025 page  Section 7 DMA Controller (DMAC) Rev. 3.00 Sep 15, 2006 page 219 of 988 REJ09B0330-0300 Bit 13—Source Address Increment/Decrement Enable (SAIDE): These bits specify whether source address register MARA is to be incremented, decremented, or left unchanged, when data transfer is performed. Bit 14 SAID Bit 13 SAIDE Description 0 0 MARA is fixed (Initial value) 1 MARA is incremented after a data transfer • When DTSZ = 0, MARA is incremented by 1 after a transfer • When DTSZ = 1, MARA is incremented by 2 after a transfer 1 0 MARA is fixed 1 MARA is decremented after a data transfer • When DTSZ = 0, MARA is decremented by 1 after a transfer • When DTSZ = 1, MARA is decremented by 2 after a transfer Bit 12—Block Direction (BLKDIR) Bit 11—Block Enable (BLKE): These bits specify whether normal mode or block transfer mode is to be used. If block transfer mode is specified, the BLKDIR bit specifies whether the source side or the destination side is to be the block area. Bit 12 BLKDIR Bit 11 BLKE Description 0 0 Transfer in normal mode (Initial value) 1 Transfer in block transfer mode, destination side is block area 1 0 Transfer in normal mode 1 Transfer in block transfer mode, source side is block area For operation in normal mode and block transfer mode, see section 7.5, Operation. Bits 10 to 7—Reserved: Can be read or written to. |
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