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HD6432351 датащи(PDF) 249 Page - Renesas Technology Corp

номер детали HD6432351
подробное описание детали  16-Bit Single-Chip Microcomputer
PDF  1025 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6432351 датащи(HTML) 249 Page - Renesas Technology Corp

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Section 7 DMA Controller (DMAC)
Rev. 3.00 Sep 15, 2006 page 215 of 988
REJ09B0330-0300
7.3
Register Descriptions (2) (Full Address Mode)
Full address mode transfer is performed with channels A and B together. For details of full address
mode setting, see table 7.4.
7.3.1
Memory Address Register (MAR)
16
*
R/W
18
*
R/W
17
*
R/W
Bit
MAR
Initial value
R/W
:
:
:
:
19
*
R/W
21
*
R/W
22
*
R/W
23
*
R/W
24
—
0
—
25
—
0
—
26
—
0
—
27
—
0
—
28
—
0
—
29
—
0
—
30
—
0
—
31
—
0
—
0
*
R/W
2
*
R/W
1
*
R/W
3
*
R/W
4
*
R/W
5
*
R/W
6
*
R/W
7
*
R/W
8
*
R/W
9
*
R/W
10
*
R/W
11
*
R/W
12
*
R/W
13
*
R/W
14
*
R/W
15
*
R/W
20
*
R/W
*: Undefined
Bit
MAR
Initial value
R/W
:
:
:
:
MAR is a 32-bit readable/writable register; MARA functions as the transfer source address
register, and MARB as the destination address register.
MAR is composed of two 16-bit registers, MARH and MARL. The upper 8 bits of MARH are
reserved: they are always read as 0, and cannot be modified.
MAR is incremented or decremented each time a byte or word transfer is executed, so that the
source or destination memory address can be updated automatically. For details, see section 7.3.4,
DMA Control Register (DMACR).
MAR is not initialized by a reset or in standby mode.
7.3.2
I/O Address Register (IOAR)
IOAR is not used in full address transfer.



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