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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HD6432351 датащи(PDF) 141 Page - Renesas Technology Corp |
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HD6432351 датащи(HTML) 141 Page - Renesas Technology Corp |
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141 / 1025 page  Section 5 Interrupt Controller Rev. 3.00 Sep 15, 2006 page 107 of 988 REJ09B0330-0300 (1) Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5.6 shows the interrupts selected in each interrupt control mode. Table 5.6 Interrupts Selected in Each Interrupt Control Mode (1) Interrupt Mask Bits Interrupt Control Mode I Selected Interrupts 0 0 All interrupts 1 NMI interrupts 2 * All interrupts Legend: *: Don’t care (2) 8-Level Control In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level. Table 5.7 Interrupts Selected in Each Interrupt Control Mode (2) Interrupt Control Mode Selected Interrupts 0 All interrupts 2 Highest-priority-level (IPR) interrupt whose priority level is greater than the mask level (IPR > I2 to I0). |
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