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HD6432351 датащи(PDF) 140 Page - Renesas Technology Corp |
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HD6432351 датащи(HTML) 140 Page - Renesas Technology Corp |
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140 / 1025 page ![]() Section 5 Interrupt Controller Rev. 3.00 Sep 15, 2006 page 106 of 988 REJ09B0330-0300 Table 5.5 Interrupt Control Modes SYSCR Interrupt Control Mode INTM1 INTM0 Priority Setting Registers Interrupt Mask Bits Description 0 0 0 — I Interrupt mask control is performed by the I bit. — 1 — — Setting prohibited 2 1 0 IPR I2 to I0 8-level interrupt mask control is performed by bits I2 to I0. 8 priority levels can be set with IPR. — 1 — — Setting prohibited Figure 5.4 shows a block diagram of the priority decision circuit. Interrupt acceptance control 8-level mask control Default priority determination Vector number Interrupt control mode 2 IPR Interrupt source I2 to I0 Interrupt control mode 0 I Figure 5.4 Block Diagram of Interrupt Control Operation |
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