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HD6432351 датащи(PDF) 134 Page - Renesas Technology Corp |
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HD6432351 датащи(HTML) 134 Page - Renesas Technology Corp |
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134 / 1025 page ![]() Section 5 Interrupt Controller Rev. 3.00 Sep 15, 2006 page 100 of 988 REJ09B0330-0300 IRQn interrupt request IRQnE IRQnF S R Q Clear signal Edge/level detection circuit IRQnSCA, IRQnSCB IRQn input Note: n: 7 to 0 Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0 Figure 5.3 shows the timing of setting IRQnF. φ IRQn input pin IRQnF Figure 5.3 Timing of Setting IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 and use the pin as an I/O pin for another function. |
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