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M32C/8A датащи(PDF) 221 Page - Renesas Technology Corp |
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M32C/8A датащи(HTML) 221 Page - Renesas Technology Corp |
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221 / 372 page ![]() M32C/8A Group 17. Serial Interfaces Rev.1.00 Jul 15, 2007 Page 204 of 352 REJ09B0385-0100 Figure 17.8 U0BRG to U4BRG Registers, U0C1 to U4C1 Registers b7 b6 b5 b4 b1 b2 b3 Symbol U0C1 to U2C1 U3C1, U4C1 Address 036Dh, 02EDh, 033Dh 032Dh, 02FDh After Reset 0000 0010b 0000 0010b b0 Function Bit Symbol Bit Name RW RE TI TE UiRRM UiLCH 0: No Data in the UiRB register 1: Data in the UiRB register Receive complete flag Data logic select bit(1) Transmit enable bit UilRS RI 0: No data in the UiTB register (TI = 1) 1: Transmit operation is completed (TXEPT = 1) 0: Not inverted 1: Inverted UARTi transmit interrupt source select bit 0: Continuous receive mode disabled 1: Continuous receive mode enabled(3) Continuous receive mode enable bit Special mode 3 Clock-divided synchronous stop bit Special mode 4 Error signal output enable bit(2) 0: Synchronization stopped 1: Synchronization started 0: Not output 1: Output SCLKSTPB UiERE UARTi Transmit/Receive Control Register 1 (i = 0 to 4) RW RO RW RO RW RW RW RW Receive enable bit 0: Receive operation disabled 1: Receive operation enabled 0: Transmit operation disabled 1: Transmit operation enabled NOTES: 1. The UiLCH bit is enabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (clock synchronous mode), 100b (UART mode, 7-bit data length), or 101b (UART mode, 8-bit data length). Set the UiLCH bit to 0 when bits SMD2 to SMD0 are set to 010b (I2C mode) or 110b (UART mode, 9-bit data length). 2. Set bits SMD2 to SMD0 before setting the UiERE bit. 3. When the UiRRM bit is set to 1, set the CKDIR bit in the UiMR register to 1 (external clock) and also disable the RTS function. UiTB register empty flag 0: Data in the UiTB register 1: No data in the UiTB register 0 b7 Symbol U0BRG to U2BRG U3BRG, U4BRG Address 0369h, 02E9h, 0339h 0329h, 02F9h After Reset Undefined Undefined b0 Function RW If the setting value is n, the UiBRG register divides a count source by n+1 00h to FFh UARTi Baud Rate Register(1, 2) (i = 0 to 4) WO Setting Range NOTES: 1. Read-modify-write instructions cannot be used to set the UiBRG register. Refer to Usage Notes for details. 2. Set the UiBRG register after setting bits CLK1 and CLK0 in the UiC0 register. |
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