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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M32C/8A датащи(PDF) 94 Page - Renesas Technology Corp |
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M32C/8A датащи(HTML) 94 Page - Renesas Technology Corp |
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94 / 372 page  M32C/8A Group 9. Clock Generation Circuits Rev.1.00 Jul 15, 2007 Page 77 of 352 REJ09B0385-0100 Figure 9.8 TCSPR Register, CPSRF Register b7 b6 b5 b4 b1 b2 b3 Count Source Prescaler Register Symbol TCSPR Address 035Fh Bit Symbol Bit Name RW CNT0 After Reset(2) 0XXX 0000b NOTES: 1. Set bits CNT3 to CNT0 after the CST bit is set to 0. 2. The TCSPR register maintains values set before reset, even after the software reset or watchdog timer reset has been performed. b0 Function Division rate select bits(1) CNT1 CNT2 If the setting value is n, f2n is the main clock, on-chip oscillator clock, or PLL clock divided by 2n. When n is set to 0, no division is selected CNT3 − (b6-b4) − RW RW RW RW CST Operation enable bit RW Reserved bits Read as undefined value 0: Divider stops 1: Divider operates Clock Prescaler Reset Register b7 b6 b5 b4 b1 b2 b3 Symbol CPSRF Address 0341h Bit Symbol Bit Name RW − (b6-b0) After Reset 0XXX XXXXb b0 Function Unimplemented. Write 0. Read as undefined value. CPSR RW − Clock prescaler reset bit When the CPSR bit is set to 1, a divider for fC32 is reset. Read as 0. |
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