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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M32C/8A датащи(PDF) 79 Page - Renesas Technology Corp |
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M32C/8A датащи(HTML) 79 Page - Renesas Technology Corp |
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79 / 372 page  M32C/8A Group 8. Bus Rev.1.00 Jul 15, 2007 Page 62 of 352 REJ09B0385-0100 8.2.4.1 Bus Cycle with Recovery Cycle Inserted The EWCRi6 bit in the EWCRi register (i = 0 to 3) determines whether the recovery cycle is inserted or not. Address output or data output is held during the recovery cycle (only when using the separate bus). Devices, which require longer address hold time or data hold time, are connectable. Figure 8.9 Recovery Cycle RD RD - Recovery cycle when separate bus is selected ( bus cycle is 1 φ + 2 φ) BCLK Address CSi Read data Write data RD WR, WRL, WRH - Recovery cycle when multiplexed bus is selected ( bus cycle is 2 φ + 3 φ) A: address LA: Latch address RD: Read data WD: Write data i = 0 to 3 NOTE: 1. When the MCU accesses the same CS area consecutively, the CSi pin keeps outputting "L". (1) Recovery cycle Address is held WD A BCLK CSi Read data Write data RD WR (WRL) ALE (1) WD LA LA Recovery cycle Data is held Data is held |
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