M32CSLASH8A datasheet(223/372 Pages) RENESAS

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M32C/8A Group

17. Serial Interfaces

Rev.1.00

Jul 15, 2007

Page 206 of 352

REJ09B0385-0100

Figure 17.10

U0TB to U4TB Registers, U0RB to U4RB Registers

Symbol

Address

After Reset

UARTi Transmit Buffer Register (1) (i = 0 to 4)

U0TB to U2TB

U3TB, U4TB

036Bh - 036Ah, 02EBh - 02EAh, 033Bh - 033Ah

032Bh - 032Ah, 02FBh - 02FAh

Undefined

Function

Bit Symbol

Transmit data (D7 to D0)

b15

−

(b7-b0)

Transmit data (D8)

−

(b8)

−

Unimplemented.

Write 0. Read as undefined value.

−

(b15-b9)

Symbol

Address

After Reset

UARTi Receive Buffer Register (i = 0 to 4)

U0RB to U2RB

U3RB, U4RB

036Fh - 036Eh, 02EFh - 02EEh, 033Fh - 033Eh

032Fh - 032Eh, 02FFh - 02FEh

Undefined

Function

Bit Symbol

Received data (D7 to D0)

b15

−

(b7-b0)

Received data (D8)

−

(b8)

−

(b10-b9)

NOTE:

1. Read-modify-write instructions cannot be used to set the UiTB register. Refer to Usage Notes for details.

Bit Name

Unimplemented.

Write 0. Read as undefined value.

0: Not detected (won)

1: Detected (lost)

Arbitration lost detect flag(1)

ABT

0: No overrun error

1: Overrun error

Overrun error flag(2)

OER

0: No framing error

1: Framing error

Framing error flag(2, 3)

FER

0: No parity error

1: Parity error

Parity error flag(2, 3)

PER

0 No error occurred

1: Error occurred

Error sum flag(2, 3)

SUM

NOTES:

1. Only a 0 can be written to the ABT bit.

2. When bits SMD2 to SMD0 in the UiMR register are set to 000b (serial interface disabled) or the RE bit in the UiC1 register is set to

0 (receive operation disabled), bits OER, FER, PER and SUM become 0.

When all of bits OER, FER and PER become 0, the SUM bit also becomes 0.

Bits FER and PER become 0 by reading the low-order byte in the UiRB register.

3. Bits FER, PER and SUM are disabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (clock synchronous mode)

or 010b (I2C mode). A read from these bits returns undefined value.

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