M16CSLASH29 datasheet(296/499 Pages) RENESAS

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16. MULTI-MASTER I2C bus INTERFACE

page 272

16.6 I2C0 Control Register 1 (S3D0 register)

The S3D0 register controls the I2C bus interface circuit.

16.6.1 Bit 0 : Interrupt Enable Bit by STOP Condition (SIM )

The SIM bit enables the I2C bus interface interrupt request by detecting a STOP condition. If the SIM bit

is set to 1, the I2C bus interface interrupt request is generated by the STOP condition detect (no need to

change in the PIN flag).

16.6.2 Bit 1: Interrupt Enable Bit at the Completion of Data Receive (WIT)

If the WIT bit is set to 1 while the ACK-CLK bit in the S20 register is set to 1 (ACK clock), the I2C bus

interface interrupt request is generated and the PIN bit is set to 1 at the falling edge of the last data bit

clock. Then an "L" signal is applied to the SCLMM and the ACK clock generation is controlled. Table 16.4

and Figure 16.12 show the interrupt generation timing and the procedure of communication restart. After

the communication is restarted, the PIN bit is set to 0 again, synchronized with the falling edge of the ACK

clock, and the I2C bus interface interrupt request is generated.

Table16.4 Timing of Interrupt Generation in Data Receive Mode

The internal WAIT flag can be read by reading the WIT bit. The internal WAIT flag is set to 1 after writing

data to the S00 register and it is set to 0 after writing to the S20 register.

Consequently, the I2C bus interface interrupt request generated by the timing 1) or 2) can be determined.

(See Figure 16.12)

When the data is transmitted and the address data is received immediately after the START condition,

the WAIT flag remains 0 regardless of the WIT bit setting, and the I2C bus interface interrupt request is

only generated at the falling edge of the ACK clock. Set the WIT bit to 0 when the ACK-CLK bit in the S20

I2C bus Interface Interrupt Generation Timing

Procedure of Communication Restart

1) Synchronized with the falling edge of the

Set the ACK bit in the S20 register.

last data bit clock

Set the PIN bit to 1.

(Do not write to the S00 register. The ACK clock

operation may be unstable.)

2) Synchronized with the falling edge of the

Set the S00 register

ACK clock

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