MSC7119 datasheet(38/60 Pages) FREESCALE

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MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

2.5.11

Event Timing

Figure 24 shows the signal behavior of the EVNT pins.

2.5.12

GPIO Timing

Figure 25 shows the signal behavior of the GPI/GPO pins.

Table 29. EVNT Signal Timing

Number

Characteristics

Type

Min

EVNT as input

Asynchronous

1.5

× APBCLK periods

EVNT as output

Synchronous to core clock

1 APBCLK period

Notes:

Refer to Table 27 for a definition of the APBCLK period.

Direction of the EVNT signal is configured through the GPIO and Event port registers.

Refer to the signal chapter in the MSC711x Reference Manual for details on EVNT pin functionality.

Figure 24. EVNT Pin Timing

Table 30. GPIO Signal Timing1,2,3

Number

Characteristics

Type

Min

601

GPI4.5

Asynchronous

1.5

× APBCLK periods

602

GPO5

Synchronous to core clock

1 APBCLK period

603

Port A edge-sensitive interrupt

Asynchronous

1.5

× APBCLK periods

604

Port A level-sensitive interrupt

Asynchronous

× APBCLK periods6

Notes:

Refer to Table 27 for a definition of the APBCLK period.

Direction of the GPIO signal is configured through the GPIO port registers.

Refer to Section 1.5 for details on GPIO pin functionality.

GPI data is synchronized to the APBCLK internally and the minimum listed is the capability of the hardware to capture data

into a register when the GPADR is read. The specification is not tested due to the asynchronous nature of the input and

dependence on the state of the DSP core. It is guaranteed by design.

The output signals cannot toggle faster than 75 MHz.

Level-sensitive interrupts should be held low until the system determines (via the service routine) that the interrupt is

acknowledged.

Figure 25. GPI/GPO Pin Timing

EVNT in

EVNT out

GPI

601

GPO

602

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