ORSPI4 datasheet(169/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

169

30B02

[0:6]

Reserved

[7]

MC_ID_ERR_INT_E

Enable for incoherent data and instruction words status ﬂag

MC_ID_ERR_STS, and associated interrupt MEM_CTRL2_INT.

30B03

[0]

MC_BURST_MODE

0 = 2-word burst

1 = 4-word burst

[1]

Reserved

[2:3]

MC_ICK_SEL

Input clock selector:

00 = MCREFCLK (HSTL)

01 = BTREFCLK (SPIA reference, LVTTL)

10 = ATREFCLK (SPIB reference, LVTTL)

11 = F_MC_REFCLK (FPGA)

[4:6]

Reserved

[7]

MC_OCK_SEL

Selects between input clock divided by 2, or PLL output for source of

PMIC/PMICN:

0 = input clock

1 = PLL

30B04

[0]

Reserved

[1:3]

PLL_N

Numerator of multiplier factor for frequency of PLL output clock:

CK2X = MC_ICK * (PLL_N / PLL_M)

[4]

Reserved

[5:7]

PLL_M

Denominator of multiplier factor for frequency of PLL Output clock:

CK2X = MC_ICK * (PLL_N / PLL_M)

30B05

[0:7}

Reserved

30B06

[0:7]

Reserved

Memory Controller Status Registers (Read Only)

30B08

[0]

MC_RD_DFIFO_UR

RUN_STS

Status ﬂag for read data FIFO underrun. Enabled by

MC_RD_DFIFO_URRUN_INT_EN

[1]

MC_RD_IFIFO_URR

UN_STS

Status ﬂag for read instruction FIFO underrun. Enabled by

MC_RD_IFIFO_URRUN_INT_EN

[2]

MC_WR_DFIFO_UR

RUN_STS

Status ﬂag for write data FIFO underrun. Enabled by

MC_WR_DFIFO_URRUN_INT_EN

[3]

MC_WR_IFIFO_URR

UN_STS

Status ﬂag for write instruction FIFO underrun. Enabled by

MC_WR_IFIFO_URRUN_INT_EN

[4]

MC_RD_DFIFO_OV

ERRUN_STS

Status ﬂag for read data FIFO overrun. Enabled by

MC_RD_DFIFO_OVERRUN_INT_EN

[5]

MC_RD_IFIFO_OVE

RRUN_STS

Status ﬂag for read instruction FIFO overrun. Enabled by

MC_RD_IFIFO_OVERRUN_INT_EN

[6]

MC_WR_DFIFO_OV

ERRUN_STS

Status ﬂag for write data FIFO overrun. Enabled by

MC_WR_DFIFO_OVERRUN_INT_EN

[7]

MC_WR_IFIFO_OVE

RRUN_STS

Status ﬂag for write instruction FIFO overrun. Enabled by

MC_WR_IFIFO_OVERRUN_INT_EN

30B09

[0:6]

Reserved

[7]

MC_ID_ERR_STS

Status ﬂag for incoherent data and instruction words. Enabled by

MC_ID_ERR_INT_EN.

30B0A

[0:7]

Reserved

Table 47. Memory Map (Continued)

(0x)

Abso-

lute

Address

Bit

Name

Reset

Value

(0x)

Description

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