ORSPI4 datasheet(151/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

151

SPIA_TXk_PORT_ID (k=32, 64, 128) signal. If M bit is not set then the port ID programmed in the TX calendar

will be broadcast to the FPGA.

• DPRAM BANK_ID ﬁeld is set to “00”.

– Address location 31003 is not used.

– Write 01 HEX to 31004 corresponding to port 1.

– Write 0F HEX to 31005 (000 to partition ID ﬁeld and 1111 to BURST_VAL ﬁeld).

– Write 0D HEX to 31006 (MB_EN bit is set to ‘1’, M bit is set to ‘1’ and DPRAM BANK_ID ﬁeld is set to “01”).

– Address location 31007 is not used.

– Write 02 HEX to 31008 corresponding to port 2.

– Write 0F HEX to 31009 (000 to partition ID ﬁeld and 1111 to BURST_VAL ﬁeld).

– Write 0E HEX to 3100A (MB_EN bit is set to ‘1’, M bit is set to ‘1’ and DPRAM BANK_ID ﬁeld is set to “10”).

– Address location 3100B is not used.

– Write 03 HEX to 3100C corresponding to port 3.

– Write 0F HEX to 3100D (000 to partition ID ﬁeld and 1111 to BURST_VAL ﬁeld).

– Write 0F HEX to 3100E (MB_EN bit is set to ‘1’, M bit is set to ‘1’ and DPRAM BANK_ID ﬁeld is set to “10”).

– Address location 3100F is not used.

This concludes the conﬁguration of the ORSPI4 SPIA Core in the dynamic mode.

In LOW SPEED STATIC mode (bit 2 of register 30915 selected) and in LOW SPEED QUARTER RATE STATIC

mode (bit 0 of register 30915 selected), the baseline procedure and the training procedure is not required. This

means that the High Speed PLL is bypassed and therefore the BIT 0 of register 30910 will always be high. In static

mode this is normal and should be ignored. In fact the only relevant bits in register 30910 are bits 6 and 7. If these

bits are not high then that means ORSPI4 has hand-shaken with another device properly.

Delay-Taps in STATIC mode

After all the conﬁguration procedure is performed, there is a possibility of ORSPI4 experiencing DIP-4 errors and

RX alignment status ﬂag being high. This can be tackled using two FPGA/CORE interface signals called

SPI_DATM_A and SPI_DLYTAP_A [2:0]. With SPI_DATM_A set to high, SPI_DLYTAP_A[2:0] should be varied from

0 to 6 to adjust the RX data with respect to RDCLK to get a valid data eye. This would help getting rid of the DIP4

errors and the RX alignment status ﬂag. This procedure is also a function of how the Board designer has laid out

the 16 RX_DATA lanes. If all the lengths are grossly mismatched then this mechanism may not work, so it is imper-

ative to design the board keeping the lengths of the RX_DATA as close as possible.

SERDES Start-Up Sequence

The following sequence is required by the SERDES. For information required for simulation that may be different

than this sequence, see the ORSPI4 Design Kit.

Initiate a hardware reset by making RESETN low. Keep this low during FPGA conﬁguration of the device. The

device will be ready for operation 3 ms after the low to high transition of RESETN.

Conﬁgure the following SERDES internal and external registers. Note that after device initialization, all alarm

and status bits should be read once to clear them. A subsequent read will provide the valid state. Set the fol-

lowing bits in register 30800:

• Bits LCKREFN_[A:D] to “1”, which implies lock to data.

• Bits ENBYSYNC_[A:D] to “1” which enables dynamic alignment to comma.

Set the following bits in register 30801:

• Bits LOOPENB_[A:D] to “1” if high-speed serial loopback is desired.

Set the following bits in registers 30002, 30012, 30022, 30032:

• TXHR set to “1” if TX half-rate is desired.

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