ORSPI4 datasheet(152/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

152

• 8B10BT set to “1”

Set the following bits in registers 30003, 30013, 30023, 30033:

• RXHR Set to “1” if RX half-rate is desired.

• 8B10BR set to “1”.

• LINKSM set to “1” if the Fibre Channel state machine is desired.

Assert GSWRST bit by writing two “1”'s. Deassert GSWRST bit by writing two “0”s. Wait 3ms. If higher speed serial

loopback has been selected, the receive PLLs will use this time to lock to the new serial data.

Monitor the following alarm bits in registers 30000, 30010, 30020, 30030:

• LKI, PLL lock indicator. “1” indicates that PLL has achieved lock.

If 8b/10b mode is enabled, enable link synchronization by periodically sending the following sequence three

times:

• K28.5 D21.4 D21.5 D21.5 or any other idle ordered set (starting with a /comma/) in FC mode.

• /comma/ characters for the XAUI state machine and /A/ characters for word and channel alignment in XAUI

Resets

Global Resets

Global resets affect all blocks in the ORSPI4 Embedded ASIC Core (EAC) section (SPIA, SPIB, MC, MPI, and

SERDES. A global reset can be caused by one the following: power-up reset, bitstream download without a partial

reconﬁguration enabled, hardware reset, or FPGA Global Set Reset (GSR).

Power-Up Reset

The power-up reset process begins when the power supply voltage ramps up to approximately 80% of the nominal

value of 1.5 V. Following this event, the device will be ready for normal operation after 3 ms. For more information

on power-up reset, please refer to the ORCA SERIES 4 FPGA data sheet at www.latticesemi.com.

Bitstream Download (DONE=0)

During bitstream download, the FPGA DONE signal remains low until the part is fully conﬁgured During this time,

all ORSPI4 EAC blocks remain in RESET. During partial reconﬁguration, an FPGA register bit can be set to prevent

a RESET of the EAC while DONE=0. For more information on bitstream conﬁguration, please refer to the ORCA

SERIES 4 FPGA data sheet at www.latticesemi.com.

Hardware Reset (RESETN)

A hardware reset is initiated by making the RESETN low for at least two microprocessor clock cycles. The device

will be ready for operation 3 ms after the low to high transition of the RESETN. This reset function affects all EAC

blocks.

FPGA Global Set Reset (GSR)

The FPGA Global Set Reset signal (GSR) can be made to reset the SPIA, SPIB and SERDES blocks of the

ORSPI4 core. This can be done during the ORSPI4 Module/IP Generation phase of the ORSPI4 core in

ispLEVER.

During this phase, the “Disable GSR from resetting data path in FPSC Core” check button is left unchecked to

enable GSR to reset these blocks. For more information on GSR, please refer to the ORCA SERIES 4 FPGA data

sheet at www.latticesemi.com.

SPIA-only Resets

The SPIA block can be individually reset though Software Reset-via the microprocessor interface, or using an

FPGA interface signal.

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