ORSPI4 datasheet(148/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

148

Any outstanding credits are cleared in the Transmit Data Path (TX_D_A)

– This is done by presetting all the Credit values in the TX credit memory to 10'h000. This is done by ﬁrst

selecting the TX credit memory by writing a ‘1’ to TX_CRED_MEM_SEL (Address 30917 in SPIA and 30A17

in SPIB) and then writing to address range 31000-310FF that correspond to locations 0 - 255 in the TX credit

memory.

– Additionally, the STAT ﬁelds for all ports must be disabled to 2'b11. This can be done by ﬁrst selecting the TX

status memory by writing a ‘1’ to TX_STAT_MEM_SEL (Address 30917 in SPIA and 30A17 in SPIB) and

then writing to address range 31000 - 310FF that correspond to locations 0 - 255 in the TX status memory.

The Data Transmitter (TX_D_A as shown in Figure 86) sends continuous Training Patterns until it receives valid

FIFO status on TX_S_A. A signal from the status block needs to be sent to the data block to indicate this. The

Transmit PDM polling is disabled at this point.

The Receive Data interface RX_D_B ignores all incoming data until it has observed the training pattern and

acquired synchronization. This can be observed by polling the RX_DSKW_DONE_STS and

RX_DSKW_ERR_STS interruptible status bits (Address 3091C in SPIA and 30A1C in SPIB). This is described

in detail in the next section. As long as the receiver is not deskewed (or synchronization is not complete),

RX_S_B will continue to send framing pattern 2’b11 on the SPI4 status link.

RX_D_B asserts DIP-4 = “OK” which is indicated by a ‘0’ on the RX_ALGN_OFF_STS interruptible status bit

(Address 3091C in SPIA and 30A1C in SPIB). This bit is set to ‘1’ if the number of consecutive DIP-4 errors

exceeds the programmed threshold. This threshold is programmed by writing to RX_DIP4_ERR_TH control

After the receiver has declared link synchronization and a calendar has been provisioned, the Receive Status

Channel RX_S_B begins sending valid FIFO status for each enabled port contained in the Calendar. Valid Sta-

tus is Frame-based with DIP-2 code words as part of the protocol. Calendar is declared as “provisioned” when

RX_CAL_LEN_MAIN (or RX_CAL_LEN_SHD if shadow calendar is being used) has a value > 0. It is recom-

mended to conﬁgure the calendar table and write the RX_CAL_LEN_MAIN last.

After the Transmitter Status Channel TX_S_A receives a conﬁgurable number of consecutive valid DIP-2 code

words, it begins transmitting data bursts of the enabled ports within the conﬁgured Calendar. The DIP-2 error

threshold can be programmed by writing to TX_DIP2_ERR_TH (Address 30944 in SPIA and 30A44 in SPIB).

At this point the end-to-end link is established and valid data/status is being transferred across the SPI4 link.

There may be cases where the Transmitter in Device “A” (TX_D_A) is active, but the Receiver in Device “B”

(RX_D_B) is in reset condition. In this situation, after the Receive Reset signal has been deasserted, the link fol-

lows the procedure deﬁned above from Step 4. When the receiver is in a reset condition, the RX_S_B block will be

sending the “1 1" framing pattern to the Transmit Status Channel interface (TX_S_A). The transmitter will follow the

procedure prescribed above as well.

There are also cases where the Data Path transmitter in Device “A” (TX_D_A) is in a reset condition, and the

Receiver in Device “B” (RX_D_B) is active. In this situation, after the Transmit Reset signal is deasserted, the link

follows the procedure deﬁned above from Step 2. When the transmitter is in a reset condition, the RX_D_B block

will not be receiving valid DIP-4 values. The RX_D_B block removes the DIP-4 = “OK” signal and the RX_S_B

block begins to send continuous “1 1" framing pattern to the Transmit Status Channel interface (TX_S_A).

SPIA or SPIB Start-up sequence

After the device is powered up, it resets itself with a Power-up reset, designed to trigger itself at power up. The ﬁrst

thing required by the ORSPI4, is to perform baseline process followed by training if dynamic alignment is chosen

(SPI4_LOW_SPEED_DATA_SEL = ‘0’). This is required by the SPIA and SPIB high-speed receivers for internal

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