ORSPI4 datasheet(150/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

150

TX_CAL_LEN_MAIN do not match the RX_CAL_M_MAIN and RX_CAL_LEN_MAIN respectively.

• It is recommended that the training be kept enabled at all times so the dynamic alignment is performed to com-

pensate for process, voltage and temperature variations.

• Program the TX_CAL_M_MAIN equal to RX_CAL_M_MAIN and TX_CAL_LEN_MAIN equal to

RX_CAL_LEN_MAIN and then the register 3091C should read 54.

• Read register 3091D twice, the ﬁrst value read could indicate DIP4 and DIP2 errors, if clears to 00 after the sec-

ond read then there are no errors. The errors during the ﬁrst read indicate that the errors existed before the train-

ing was performed.

• Read the register 3090A to read the DIP4 error count. This register will keep counting if the bit 5 of 3091D is set,

otherwise this register will show 00.

• Read the register 3090B to read the DIP2 error count. This register will keep counting if the bit 6 of 3091D is set,

otherwise this register will show 00.

After the above conﬁguration is completed, the device is not yet ready to transmit and receive data. The user still

has to provision the Calendars and the Port Descriptor Memories for appropriate bandwidth. This is an indirect

addressing mechanism where a single bit in register 30917 selects which memory space needs to be addressed.

Once one of the bit is selected then the user can write to 31000 to 31FFF address space. The following example

shows how to program TX PDM, RX PDM, TX calendar and RX calendar.

• Four ports (0, 1, 2 and 3) of SPI4 data with equal bandwidth.

• No DPRAM Partitions (Virtual FIFOs).

• Write 20 HEX to 30917 to select the RX calendar indirect addressing

• Next program the RX calendar memory through the following writes:

– Write 00 to the 31000 location.

– Write 01 to the 31001 location.

– Write 02 to the 31002 location.

– Write 03 to the 31003 location.

• Write 10 HEX to register 30917 to select the RX PDM indirect addressing. Since there are no partitions for the

DPRAMS, only the bits which correspond to the BANK_ID of the DPRAMs will be written. Bits that correspond to

the PARTITION_ID of the DPRAMs are written to “000”.

– Write 00 HEX to the 31000 location which means that data will read from the DPRAM0 for port 0.

– Write 08 HEX to the 31001 location which means that data will be read from the DPRAM1 for port 1.

– Write 10 HEX to the 31002 location which means that data will be read from the DPRAM2 for port 2.

– Write 18 HEX to the 31003 location which means that data will be read from the DPRAM3 for port 3.

• Write 08 HEX to 30917 to select the TX calendar indirect addressing

– Write 00 to the 31000 location.

– Write 01 to the 31001 location.

– Write 02 to the 31002 location.

– Write 03 to the 31003 location.

• Write 04 HEX to 30917 to select the TX PDM indirect addressing. TX PDM has a total of 6 ﬁelds to be written and

they are divided into 3 bytes. These three bytes correspond to a single memory location for TX PDM, which has

a total of 256 locations.

– Write the port ID 00 HEX to 31000 corresponding to port 0.

– Write 0F HEX to 31001 (000 to partition ID ﬁeld and 1111 to BURST_VAL ﬁeld).

– Write 0C HEX to 31002 which implies:

• MB_EN bit is set to ‘1’ which means that MAX-BURST1 and MAX-BURST2 both will be supported, otherwise

only MAX-BURST1 will be used.

• M bit is set to ‘1’ which means the port ID ﬁeld programmed in the TX PDM is propagated to the FPGA on the

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