ORSPI4 datasheet(149/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

149

alignment. Dynamic alignment may also be required during normal transmission and reception of SPI4 data

because Process, Voltage and Temperature variations can alter the alignment.

The procedure is as follows (only shown for SPIA)

• Enable the interrupts related to the high-speed receive interface block by writing FF to 30913. This would enable

the status update on the register 3091C. It is also recommended to enable other interrupts as well. For example

registers 30912 and 30914 so that the corresponding statuses can be monitored.

• Set register 30910 to 0x71 this would set the DIP4 Error threshold to 7 and will enable baseline for SPIA to per-

form “ORSPI4 baseline” procedure. DIP4 Error threshold is set to 7 for experimental reasons only, most of the

applications engineers would want to set it to 1 to ﬂag any single DIP4 error.

• Soft-reset the SPIA core by writing 0x02 to 30B20 and then clearing this bit. This can also be achieved by pulsing

the s4a_fpga_reset FPGA/CORE interface pin. Please note that every time the ORSPI4 core is soft-reset the

TXPDM contents are erased whereas the contents of RXPDM, RXCAL and TXCAL remain intact. Software engi-

neers would want to put a state machine in the API to reprogram the TXPDM once the soft reset is pulsed. Soft

reset may be required to pulse if because of any reason ORSPI4 loses its synchronization with another device. In

that case “ORSPI4 baseline” procedure needs to be performed again by pulsing the soft reset.

• Read the 3091C register - it should read 0x53

– Bit 0 = 0 indicates that the RDI PLL has locked to the REFCLKA. If the RDCLK (SPI4 receive clock) is

present then the PLL will lock to the RDCLK.

– Bit 1 = 1 indicates that the Baseline has been done

– Bit 2 = 0 indicates that there are no Baseline errors

– Bit 3 = 1 indicates that receive de-skew has been achieved. This bit will stay high if the enable training is not

set in the register 30910, it will also be set once the training has been done.

– Bit 4 = 0 indicates that there are no receive de-skew errors, these errors will only show up if the training has

been enabled and de-skewing is not successful.

– Bit 5 = 0 indicates that training is not detected

– Bit 6 = 1 indicates that byte-lanes' alignment is off, this bit is also relevant if the training is enabled and Bytes

are not being aligned properly.

– Bit 7 = 1 indicates that the TX status is showing LOF, because the TX_CAL_M_MAIN and

TX_CAL_LEN_MAIN do not match the RX_CAL_M_MAIN and RX_CAL_LEN_MAIN respectively.

• Enable internal loopback by writing 0x08 to 30915. This is only required if there is no other SPI4 device talking to

ORSPI4. External loopback can also be performed in which case this register bit should not be set.

• Program the TX_DATA_MAX_T and TX_ALPHA values in the registers 30935, 30936, 30937, 30940, 30941 and

30942. Setting a non-zero value to these registers will automatically cause the transmit block to initiate the SPI4

training sequence.

• Program the RX_FIFO_THRESHOLD_H (30911) and TX_FIFO_THRESHOLD_H (30945) values to 0x78 and

0x17 respectively. These are watermarks for internal asynchronous FIFOs. These are the recommended values.

If MINBURST mode is desired then TX_FIFO_THRESHOLD_H needs to be set appropriately. Refer to MIN-

BURST MODE section of the data sheet.

• Keep baseline enabled and, enable training by writing 0x73 to 30910.

• Read the 3091C register and it should read 0x55

– Bit 0 = 0 indicates that the receive PLL has locked to REFCLKA or RDCLK.

– Bit 1 = 1 indicates that the Baseline has been done

– Bit 2 = 0 indicates that there are no Baseline errors

– Bit 3 = 1 indicates that RDI de-skew has been achieved

– Bit 4 = 0 indicates that there are no RDI de-skew errors

– Bit 5 = 1 indicates that training is detected.

– Bit 6 = 0 indicates that byte-lanes' alignment is not off.

– Bit 7 = 1 indicates that the TX status is showing LOF, because the TX_CAL_M_MAIN and

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