ORSPI4 datasheet(147/263 Pages) LATTICE

147 / 263 page

Lattice Semiconductor

ORCA ORSPI4 Data Sheet

147

Software

Software for Conﬁguration

There are two ways to write to the ORSPI4 memory map either via MPI (Microprocessor Interface) or via UMI (User

Master Interface) to the FPGA logic. Both the interfaces use the system bus to perform the transactions with the

registers. The MPI is provided to talk to any Power PC microprocessor whereas UMI is used for any customer-

deﬁned interface and interfaces extremely well with ORCASTRA™ to graphically change and monitor the register

map. The registers are divided into different domains, the details of which can be found in the technical note

TN1017. ORSPI4 device core registers can be accessed by addressing the 30000 onwards domain. Since there

are four different macros inside the ORSPI4 core, all these macros have been assigned their individual sub

domains.

Table 43. Address Allocation - Register Elements

ORSPI4 Start-up Sequence

SPI4 Link Start-up Protocol

Immediately after reset, and before the link synchronization, the SPI4 link must initialize to a known interface proto-

col. This section describes the initialization protocol for a generic SPI4 link. The actual start-up procedure with the

appropriate software register settings is described in the next section. Figure 86 shows the SPI4 link reference dia-

gram that is referenced in the descriptions below. Where appropriate, the corresponding ORSPI4 software register

settings are also described as relevant to this start-up protocol.

A reset can be either hard or soft, but is assumed that the entire SPI4 link is being reset. Immediately after the

reset signal is deasserted and before the link synchronization, the following actions/conditions must occur/exist.

Figure 86. SPI4 Link Functional Block Diagram

The Receive Data FIFOs are emptied (RX_D_B)

Address (0x)

Description

309xx

SPIA addresses

30Axx

SPIB addresses

308xx

SERDES addresses

30Bxx

QDR MEM controller addresses and

some shared by SPIA and SPIB

Device A

Device B

TX_D_A

RX_D_B

RX_S_B

TX_S_A

DIP2 = “OK”

DIP4 = “OK”

ORSPI4 датащи(PDF) 147 Page - Lattice Semiconductor

ORSPI4 датащи(HTML) 147 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL