ST72411R datasheet(38/71 Pages) STMICROELECTRONICS

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ST72411R

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8-BIT TIMER (Cont’d)

5.3.5 Register Description

PRESCALER COUNTER REGISTER (PSCR)

Read only

Reset Value: 1111 1111 (FFh)

Bit 7:0 = PSCR[8:1]

Prescaler MSB.

TIMER COUNTER REGISTER (TCR)

Read / Write

Reset Value: 1111 1111 (FFh)

Bit 7:0 = TCR[7:0]

Timer counter bits.

TIMER STATUS CONTROL REGISTER (TSCR)

Read/Write

Reset Value: 0101 0000 (50h)

Bit 7 = OEN

Output Enable.

In output mode, this bit allows DOUT to be send to

the timer output. It has no effects in INPUT mode.

0: Output disabled (reset state)

1: Output enabled

Bit 6 = TOUT

Timer Output Control.

When low, this bit selects the input mode for the

TIMER pin. When high the output mode is select-

ed.

0: Input mode

1: Output mode (reset state)

Bit 5 = DOUT

Data Output.

Data sent to the timer output when UDF is set high

(output mode only). Input mode selection (input

mode only).

Bit 4 = UDF:

Timer Underflow.

A low-to-high transition indicates that the timer

count register has underflowed. It means that the

TCR value has changed from 00h to FFh.

This bit must be cleared by user software.

0: Counter has not underflowed

1: Counter underflow occurred (reset state)

Bit 3 = ETI:

Enable Timer Interrupt.

When set, enables the timer interrupt request. If

ETI=0 the timer interrupt is disabled. If ETI=1 and

UDF=1 an interrupt request is generated.

0: Interrupt disabled (reset state)

1: Interrupt enabled

Bit 2 = PSE:

Prescaler Enable.

Used to initialize the prescaler and inhibit its count-

ing. When PSE=“0” the prescaler is set to 1FFh

and the counter is inhibited. When PSE=“1” the

prescaler is enabled to count downwards. As long

as PSE=“0” both counter and prescaler are not

running

0: Counting disabled (reset state)

1: Counting enabled

Bit 1:0 = PS1:0

Prescaler Mux. Select.

These bits select the division ratio of the prescaler

PSCR8 PSCR7 PSCR6 PSCR5 PSCR4 PSCR3 PSCR2 PSCR1

TCR7

TCR6

TCR5

TCR4

TCR3

TCR2

TCR1

TCR0

OEN

TOUT

DOUT

UDF

ETI

PSE

PS1

PS0

fTIMER divided by

PS1

PS0

512

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