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ST72411R датащи(PDF) 19 Page - STMicroelectronics |
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ST72411R датащи(HTML) 19 Page - STMicroelectronics |
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19 / 71 page ![]() ST72411R 19/71 RESET MANAGER (Cont’d) ([ W HUQDO5( 6 ( 7 SLQ The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor (see Figure 11). This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the de- vice. A RESET signal coming from an external source must have a duration of at least tPULSE in order to be recognized. Two RESET sequences can be as- sociated with this RESET source as shown in Fig- ure 12. When the RESET is generated by an internal source, during the two first phases of the RESET sequence, the device RESET pin acts as an out- put that is pulled low. Figure 12. External RESET Sequence with internal Clock Selected (OSC_SEL pin tied to VSS) Figure 13. External RESET Sequence with External Clock Selected (OSC_SEL pin tied to VDD) 5( 6 ( 7 58 1 INTERNAL RESET 4096 CLOCK CYCLES FETCH VECTOR 58 1 tPULSE 9 ’’ VIT+ VDD nominal DELAY RESET PIN EXTERNAL RESET SOURCE 5( 6 ( 7 58 1 INTERNAL RESET 260 CLOCK FETCH VECTOR 58 1 tPULSE 9 ’’ VIT+ VDD nominal DELAY LVDS, ON OFF OPSD, PSS 4096 CLOCK CYCLES CYCLES ON RESET PIN EXTERNAL RESET SOURCE |
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