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ST72411R датащи(PDF) 18 Page - STMicroelectronics |
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ST72411R датащи(HTML) 18 Page - STMicroelectronics |
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18 / 71 page ![]() ST72411R 18/71 3.2 RESET SEQUENCE MANAGER The RESET sequence manager includes two re- set sources as shown in Figure 11: s External RESET source pulse s Internal LVDS RESET (Low Voltage Detection) These sources act on the RESET PIN and it is al- ways kept low during the delay phase. The RESET service routine vector is fixed at ad- dresses FFFEh-FFFFh in the ST7 memory map. A 4096 CPU clock cycle delay allows the oscillator to stabilise and to ensure that recovery has taken place from the Reset state. The RESET vector fetch phase duration is 2 clock cycles. Figure 11. Reset Block Diagram fCPU RESET RON VDD LVD RESET INTERNAL RESET |
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