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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72411R датащи(PDF) 32 Page - STMicroelectronics |
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ST72411R датащи(HTML) 32 Page - STMicroelectronics |
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32 / 71 page  ST72411R 32/71 5.2 MISCELLANEOUS REGISTER The miscellaneous register allows control over several features such as the external interrupts or the I/O alternate functions. 5.2.1 I/O Port Interrupt Sensitivity Description The external interrupt sensitivity is controlled by the IPB and IS[1:0] bits of the Miscellaneous regis- ter (Figure 23). Up to 2 fully independent external interrupt source sensitivities are allowed. Each external interrupt source can be triggered by four different events on the pin: s Falling edge s Rising edge s Falling and rising edge s Falling edge and low level To guarantee the functionality, a modification of the sensitivity in the MISC register can be done only when the I bit of the CC register is set to 1 (in- terrupt masked). See I/O port register and Miscel- laneous register descriptions for more details on programming. Caution: Take care when changing the value of the IPB bit as, in some cases, an interrupt will be generated by the edge resulting from the change. 5.2.2 Slow mode and VDD Supply Monitoring The MISCR register manages SLOW mode selec- tion and the LVDS VDD monitoring interrupt. Refer to the register description. Figure 23. External Interrupt Sources vs MISCR EI1 INTERRUPT SOURCE EI0 INTERRUPT SOURCE IS0 IS1 MISCR SENSITIVIT Y CONTROL PB6 IPB PB0 SOURCES PA7 PA0 SOURCES |
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