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MK50H25PLCC датащи(PDF) 53 Page - STMicroelectronics

номер детали MK50H25PLCC
подробное описание детали  HIGH SPEED LINK LEVEL CONTROLLER
PDF  64 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

MK50H25PLCC датащи(HTML) 53 Page - STMicroelectronics

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A 16-23
ALE
SYSCLK
BM0,1
READY
DAS
HLDA
HOLD
64
24
25
65
26
27
40
23
23
44
41
42
28
22
T1
T2
T 3
T4
T 5
DAL0-15
READ
DALO
DALI
29
30
50
32
45
DATA IN
ADDR
31
49
48
47
46
48
ADDRESS
60
61
43
NOTES:
2. Output delay times are the maximum delay from the specifed edge to a valid output.
3. The Bus Master cycle time will increase from a minimum, in 1 SYSCLK increments
until the slave device returns READY.
1. This reduced DMA Cycle Time is selected by setting CSR2 bit 15, CYCLE =1.
Figure 7a: MK50H25 Reduced Cycle BUS Master Timing (Read) (for CYCLE = 1, CSR2<15>)
MK50H25
53/64



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