MK50H25PLCC datasheet(22/64 Pages) STMICROELECTRONICS

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07:00

IADR

The high order 8 bits of the address of the first word (lowest address)

in the Initialization Block. IADR must be written by the Host prior to

issuing an INIT primitive.

4.1.2.4 Control and Status Register 3 (CSR3)

RAP<3:1> = 3

BIT

NAME

DESCRIPTION

15:00

IADR

The low order 16 bits of the address of the first word (lowest address)

in the Initialization Block. Must be written by the Host prior to issuing

an INIT primitive. The Initialization block must begin on an even byte

boundary.

4.1.2.5 Control and Status Register 4 (CSR4)

CSR4 allows redefinition of the bus master interface.

RAP<3:1> = 4

BIT

NAME

DESCRIPTION

15:12

XWD0/1, RWD0/1

These bits enable and determine the timer values for the Transmit and

Receive Watchdog Timers. These timers are independently program-

mable and are reset by any transition on the TCLK and RCLK pins re-

spectively. The Watchdog timers will expire after approximately Wn

SYSCLK cycles (if not reset by transition on TCLK / RCLK pins) and

Provider Primitive 3 will be issued. The following table shows the se-

lections for Wn:

XWD1/RWD1

XWD0/RWD0

Disabled

ROBA

Setting this bit will cause the MK50H25 to put the first byte of received

data into both the upper and lower bytes of the receive buffer to effec-

tively cause the Receive data to be Odd-Byte Aligned. This feature is

particularly useful for extraction of odd-byte Level 3 headers from re-

ceived frames leaving the remaining data even byte aligned.

XHOLD

Setting this bit enables the Transmit FIFO Hold-off mechansim of the

MK50H25. The Transmit FIFO Hold-off watermark is selected along

with the FIFO watermark so as to avoid possible conflicts.

IADR <15:00>

MK50H25

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