MK50H25PLCC datasheet(23/64 Pages) STMICROELECTRONICS

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09:08

FWM

These bits define the FIFO watermarks. FIFO watermarks prevent the

MK50H25 from performing DMA transfers to/from the data buffers until

the FIFOs contain a minimum amount of data or space for data. For re-

ceive, data will only be transferred to the buffers after the FIFO has at

least N 16-bit words or end of frame has been reached. Conversely, for

transmit, data will only be transferred from the data buffers when the

transmit FIFO has room for at least N words of data. The Transmit

Threshold FIFO Watermark is also defined by these bits. If enabled by

setting XHOLD=1, the transmitter will be held-off from transmitting a

new frame until the transmit FIFO has at least N words of data, or the

entire frame has been placed in the FIFO. The N is defined as follows:

FWM<1:0>

FWM N

XHOLD N

Not Allowed

* Suggested setting

10*

9 words

19 words

17 words

11 words

25 words

3 words

BAE

Bus Address Enable: If BAE is set, the A23-A20 pins are driven by the

MK50H25 constantly providing the ability to use A23-A20 for memory

bus selection. If clear, A23-A20 behave identically to A19- A16.

BUSR

If this bit is set, pin 15 becomes input BUSREL. If this bit is clear

then pin 15 is either BM0 or BYTE depending on bit 00. For more in-

formation see the description for pin 15 in this document. BUSR is

READ/WRITE and cleared on bus Reset.

BSWPC

This bit determines the byte ordering of all ”non-data” DMA transfers.

This transfers refers to any DMA transfers that access memory other

than the data buffers themselves. This includes the Initialization Block,

Descriptors, and Status Buffer. It has no effect on data DMA transfers.

BSWPC allows the MK50H25 to operate with memory organizations

that have bits 07:00 at even addresses and with bits 15:08 at odd ad-

dressses or vice versa. BSWPC is Read/Write and cleared by BUS

RESET.

With BSWPC = 1:

Address

With BSWPC = 0:

Address

04:03

BURST

This field determines the maximum number of data transfers performed

each time control of the host bus is obtained. BURST is READ/WRITE

and cleared on bus Reset.

* Suggested setting

BSWPD

This bit determines the byte ordering of all data DMA transfers.

Data transfers are those to or from a data buffer. BSWPD has no ef-

fect on non-data transfers. The effect of BSWPD on data transfers is

the same

that

BSWPC on non-data transfers

(see

above). For most applications, this bit should be set.

XX0

. . .

8. . .

XX0

XX1

. . .

8. . .

XX1

BURST <1:0>

8 bit mode

16 bit mode

2 bytes

1 words

10*

16 bytes

8 words

unlimited

MK50H25

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