MK50H25PLCC datasheet(34/64 Pages) STMICROELECTRONICS

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14:12

TLEN

TRANSMIT RING LENGTH is the number of entries in the Transmit

Ring expressed as a power of two.

TLEN

NUMBER

ENTRIES

TWD

WINDOW SIZE

EXTC = 0

EXTC = 1

128

127

Reserved, must be written as a zero.

10:08

TWD

Transmit Window is the window size of the Transmitter expressed as a

power of two less one. TWD is the maximum number of I frames which

may be transmitted without an acknowledgement. TWD is not allowed

to be greater than 127. For Transparent Mode set TWD = 1 or more.

07:00/15:00

TDRA

TRANSMIT DESCRIPTOR RING ADDRESS is the base address

(lowest address) of the Transmit Descriptor Ring. The Transmit De-

scriptor Ring Address must begin on a word boundary.

4.2.7 XID/TEST Descriptors

The XID/TEST Descriptors contain pointers to the buffers used to receive and transmit XID, and TEST

frames, as well as buffer lengths. The exact format of these descriptors can be seen in the following Re-

ceive and Transmit Message Descriptor Entry descriptions. They are used the same as other descriptors

except that no data chaining is allowed (i.e., SLF and ELF must be set to 1).

4.2.8 Status Buffer Address

BIT

NAME

DESCRIPTION

15:08

Reserved, must be written as zeroes.

07:00/15:00

SBA

STATUS BUFFER ADDRESS points to a 7 word status

buffer into which status information is placed upon the issuance of the

Status Request primitive by the HOST. The status buffer must begin

on a word boundary.

IADR + 40

IADR + 42

SBA<15:00>

SBA<23:16>

(If CSR2 EIBEN =1)

MK50H25

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