MK50H25PLCC datasheet(17/64 Pages) STMICROELECTRONICS

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INEA

INTERRUPT ENABLE allows the INTR I/O pin to be driven low when

the Interrupt Flag is set. If INEA = 1 and INTR = 1 the INTR I/O pin will

be low. If INEA = 0 the INTR I/O pin will be high, regardless of the

state of the Interrupt Flag.

INEA is READ/WRITE set by writing a

”1” into this bit and is cleared by writing a ”0” into this bit, by Bus RE-

SET, or by issuing a Stop primitive. INEA may not be set while in the

Stopped phase.

INTR

INTERRUPT FLAG indicates that one or more of the following interrupt

causing conditions has occurred: MISS, MERR, RINT, TINT, PINT,

TUR or ROR. If INEA = 1 and INTR = 1 the INTR I/O pin will be low.

INTR is READ ONLY, writing this bit has no effect. INTR is cleared as

the specific interrupting condition

bits are cleared.

INTR is also

cleared by Bus RESET or by issuing a Stop primitive.

MERR

MEMORY ERROR is set when the MK50H25 is the Bus Master and

READY has not been asserted within 256 SYSCLKs (25.6 usec @

10MHz) after asserting the address on the DAL lines. When a Mem-

ory

Error

is detected, the MK50H25 releases the bus, the receiver

and transmitter are turned off, and an interrupt is generated if INEA =

1. MERR is READ/CLEAR ONLY and is set by the chip and cleared by

writing a ”1” into the bit. Writing a ”0” has no effect.

It is cleared by

Bus RESET or by issuing a Stop primitive.

MISS

MISSED frame is set when the receiver loses a frame because it does

not own a receive buffer indicating loss of data. When MISS is set,

RXON is cleared and an interrupt will be generated if INEA = 1. If

MISS is set while a data link is established, the MK50H25 will go into

the Local Busy state and will send an RNR response frame to the re-

mote station. Upon clearing MISS the MK50H25 will send a RR re-

sponse frame. MISS is READ/CLEAR ONLY and is set by MK50H25

and cleared by writing a ”1” into the bit. Writing a ”0” has no effect. It

is also cleared by Bus RESET or by issuing a Stop primitive.

ROR

RECEIVER OVERRUN indicates that the Receiver FIFO was full when

the receiver was ready to input data to the Receiver FIFO. When ROR

occurs, the receive FIFO will be flushed and the buffer(s) containing

any part of the frame already received will be re-used by the next in-

comming frame. Therefore, the frame being received is lost, but is typi-

cally recoverable through the protocol used. When ROR is set, an in-

terrupt is generated if INEA = 1. ROR is READ/CLEAR ONLY and

is set by MK50H25 and cleared by writing a ”1” into the bit. Writing a

”0” has no effect. It is also cleared by Bus RESET or by issuing a Stop

primitive.

TUR

TRANSMITTER UNDERRUN indicates that the MK50H25 has aborted

a frame since data was late from memory. This condition is reached

when the transmitter and transmitter FIFO both become empty while

transmitting a frame. The frame in transmission at the time will be

aborted. When TUR is set, an interrupt is generated if INEA = 1. TUR

is READ/CLEAR ONLY and is set by MK50H25 and cleared by writing

a ”1” into the bit. Writing a ”0” has no effect. It is also cleared by Bus

RESET or by issuing a Stop primitive.

PINT

PRIMITIVE INTERRUPT is set after the chip updates the primitive

generated if INEA =1.

PINT is READ/CLEAR ONLY and is set by

MK50H25 and cleared by writing a ”1” into the bit. Writing a ”0” has no

effect. It is also cleared by Bus RESET or by issuing a Stop primitive.

TINT

TRANSMITTER INTERRUPT is set after the chip updates an entry in

the Transmit Descriptor Ring. This occurrs when a transmitted I frame

has been acknowledged by the remote station. When transmitting UI

frames, or in Transparent Mode, TINT is set upon completing transmis-

sion of the frame. When TINT is set, an interrupt is generated if INEA

= 1. TINT is READ/CLEAR ONLY and is set by the MK50H25 and

MK50H25

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