MK50H25PLCC datasheet(27/64 Pages) STMICROELECTRONICS

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4.2.1 Mode Register

The Mode Register allows alteration of the MK50H25’s operating parameters.

BIT

NAME

DESCRIPTION

15:11

MFS<4:0>

Minimum Frame Spacing defines the minimum number of flag

sequences transmitted

between adjacent frames transmitted by the

MK50H25. This only affects frames transmitted by the MK50H25

and does not restrict the spacing of the frames received by the

MK50H25.

When

using RTS/CTS control this field defines the

number of flags

transmitted at the beginning of the frame after

CTS is driven low (minus one for the trailing flag). See the following

table for encoding of this field.

EXTCF

Extended Control Force. If set along with EXTC, the receiver will assume

the control field to be two octets long regardless of the first two bits of

the control field. See EXTC below.

EXTAF

Extended Address Force. If set along with EXTA, the receiver will

assume the address to be two otets long regardless of the first bit of

the address. See EXTA below.

DACE

Address and control field extraction are disabled when DACE is set

Address and control fields are treated as data and placed in memory

as such. DACE must be written with ”1” for normal transparent data

transfer operation, but can be set to ”0” for doing address and control

field filtering.

EXTC

Extended Control Field filtering is enabled when EXTC = 1 if DACE = 0

and PROM = 0 (PROM is in CSR2).

EXTA

Extended Address Field filtering is enabled when EXTA = 1 if DACE = 0

and PROM = 0 (PROM is in CSR2).

DRFCS

Disable Receiver FCS (CRC). When DRFCS = 0, the receiver will extract

and check the FCS field at the end of each frame. When DRFCS = 1,

the receiver continues to extract the last 16 or 32 bits of each frame,

LBACK

<2:0>

MFS

<4:0>

IADR + 00

NUMBER OF FLAGS

MFS<4:0>

NUMBER OF FLAGS

MFS<4:0>

MK50H25

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