MK50H25PLCC datasheet(33/64 Pages) STMICROELECTRONICS

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4.2.5 Receive Descriptor Ring Pointer

BIT

NAME

DESCRIPTION

RINTD

RECEIVE INTERRUPT DISABLE. Setting this bit will cause no Receive

Interrupt (RINT) to be generated upon the reception of any frame.

14:12

RLEN

RECEIVE RING LENGTH is the number of entries in the Receive

Ring expressed as a power of two.

RBSY

Remote Busy indication enable. Setting this bit will enable the issuance

of Remote Busy Indication primitives (PPRIM=5) upon reception of

RNR or RR frame indicating a change in the busy status of the remote.

RBFCS

Receive frames with Bad FCS. Setting this bit causes the MK50H25 to

receive frames with bad FCS when in Transparent Mode. The FRMRR

bit in RMD0 will be set to indicate the received frame had a bad FCS.

This bit should be set only for Transparent Mode

FCSER

FCSER. Setting this bit enables a separate Error Counter at IADR + 56

that will count aborted frames separately from Bad Frames Received.

FCSEN

Setting this bit will cause the MK50H25 to append the entire FCS of

received frames to the receive data buffer, and MCNT will reflect the

additional FCS bytes.

07:00/15:00

RDRA

RECEIVE DESCRIPTOR RING ADDRESS is the base address

(lowest address) of the Receive Descriptor Ring. The Receive De-

scriptor Address must begin on a word boundary.

4.2.6 Transmit Descriptor Ring Pointer

BIT

NAME

DESCRIPTION

Reserved, must be written as a zero.

IADR + 16

IADR + 18

RDRA<15:00>

RLEN

RDRA<23:16>

IADR + 20

IADR + 22

TDRA<15:00>

TLEN

TDRA<23:16>

TWD

MK50H25

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