M7040N datasheet(38/159 Pages) STMICROELECTRONICS

38 / 159 page

M7040N

38/159

Table 24. WRITE Address Format for Internal Registers

Table 25. WRITE Address Format for Data and Mask Array (Burst Write)

Parallel WRITE

In order to write the data and mask arrays faster

for initialization, testing, or diagnostics, many loca-

tions can be written simultaneously in the M7040N

device. When CMD[9] is set in Cycles A and B of

the WRITE command during a WRITE to the data

or mask arrays, the address present on DQ[10:1]

that specifies 64 locations in a device is used and

64 72-bit locations are simultaneously written in ei-

ther the data or mask array.

SEARCH COMMAND

The M7040N (Silicon) Search Engine can be con-

figuredinfour ways:

1. 72-bit

2. 144-bit (page )

3. 288-bit (page )

4. Mixed-sizes on tables configured with differ-

ent widths using an M7040N with CFG_L low

or CFG_L high (page )

72-bit Configuration with Single Device

The hardware diagram of the search subsystem of

a single device is shown in Figure 22. Figure 23,

page 40 shows the timing diagram for a SEARCH

operation in the 72-bit configuration (CFG =

0000000000000000) for one set of parameters.

This illustration assumes that the host ASIC has

programmed TLSZ to '00,' HLAT to '000,' LRAM to

'1,' and LDEV to '1' in the command register.

The following is the sequence of operations for a

single 72-bit SEARCH command.

– Cycle A: Thehost ASICdrives CMDV highand

applies the SEARCH command code ('10') on

CMD[1:0] signals. {CMD[10], CMD[5:3] must be

driven with the index to the global mask register

pair for use in the SEARCH operation. CMD[8:6]

signals must be driven with the same bits that

will be driven on SADR[23:21] by this device if it

has a hit. DQ[71:0] must be driven with the 72-

bit data to be compared. The CMD[2] signal

must be driven to Logic '0.'

– Cycle B: The host ASIC continues to drive

CMDV high and applies the SEARCH command

('10') on CMD[1:0]. CMD[5:2] must be driven by

the index of the comparand register pair for stor-

ing the 144-bit word presented on the DQ Bus

during Cycles A and B. CMD[8:6] signals must

be driven with the index of the SSR that will be

used for storing the address of the matching en-

try and the Hit Flag (see SEARCH-Successful

Registers (SSR[0:7]), page 24). The DQ[71:0]

continues to carry the 72-bit data to be com-

pared.

Note: In the 72-bit configuration, the host ASIC

must supply the same data on DQ[71:0] during

both Cycles A and B. The even and odd pair of

GMRs selected for the comparison must be pro-

grammed with the same value.

DQ[71:26]

DQ[25:21]

DQ[20:19]

DQ[18:7]

DQ[6:0]

Reserved

11: Register

Reserved

[71:26]

[25:21]

[20:19]

[18:16]

[15:0]

Reserved

00: Data array

Reserved

Don’t care. These 16 bits come from the internal

access.

Reserved

01: Mask

array

Reserved

Don’t care. These 16 bits come from the internal

access.

M7040N датащи(PDF) 38 Page - STMicroelectronics

M7040N датащи(HTML) 38 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL