M7040N datasheet(23/159 Pages) STMICROELECTRONICS

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M7040N

Comparand Registers

The device contains 32 72-bit comparand regis-

ters (16 pairs) dynamically selected in every

SEARCH operation to store the comparand pre-

sented on the DQ Bus. The LEARN command will

later use these registers when executed. The

M7040N stores the SEARCH command’sCycle A

comparand in the even-numbered register and the

Cycle B comparand in the odd-numbered register,

as shown in Figure 13.

Figure 13. Comparand Register Selection

During SEARCH and LEARN

Instructions

Mask Registers

The device contains 32 72-bit global mask regis-

ters (16 pairs) dynamically selected in every

SEARCH operation to select the search subfield.

The addressing of these registers is explained in

Figure 14. The four-bit GMR Index supplied on the

command (CMD) bus can apply 16 pairs of global

masks during the SEARCH and WRITE opera-

tions, as shown below.

Note: In 72-bit SEARCH and WRITE operations,

the host ASIC must program both the even and

odd mask registers with the same values.

Each mask bit in the GMRs is used during

SEARCH and WRITE operations. In SEARCH op-

erations, setting the mask bit to '1' enables com-

pares; setting the mask bit to '0' disables

compares (forced match) at the corresponding bit

position. In WRITE operations to the data or mask

array, setting the mask bit to '1' enables WRITEs;

setting the mask bit to '0' disables WRITEs at the

corresponding bit position.

Figure 14. Addressing the Global Masks

143

Address

Index

AI04667

143

Address

Index

AI04668

SEARCH and WRITE Command

Global Mask Selection

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