M7040N datasheet(35/159 Pages) STMICROELECTRONICS

35 / 159 page

35/159

M7040N

Table 21. READ Address Format for Internal Registers

Table 22. READ Address Format for Data and Mask Arrays

WRITE COMMAND

TheWRITE canbea singlewrite of adata array,

mask array, register, or external SRAM location

(CMD[2] =

0). It can

burst WRITE

(CMD[2] = 1) using an internal auto-incrementing

address register (WBURADR) of the data array or

mask array locations. A single-location WRITE is a

three-cycle operation, shown in Figure 20, page

36. The burst WRITE adds one extra cycle for

each successive WRITE.

The WRITE operation sequence is as follows:

– Cycle 1A: The host ASIC applies the WRITE In-

struction on the CMD[1:0] (CMD[2] = 0), using

CMDV=1 and the address supplied on the DQ

Bus, as shown in Table 23, page 37. The host

ASIC also supplies the index to the global mask

mask array location in {CMD[10], CMD[5:3]}.

For SRAM WRITEs, the host ASIC must supply

the SADR[23:21] on CMD[8:6]. The host ASIC

sets CMD[9] to '0' for the normal WRITE.

– Cycle 1B: The host ASIC continues to apply the

WRITE

Instruction

the

CMD[1:0]

(CMD[2] = 0), using CMDV = 1 and the address

supplied on the DQ Bus. The host ASIC contin-

ues to supply the global mask register index to

mask the WRITE to the data or mask array loca-

tions in {CMD[10], CMD[5:3]}. The host ASIC

selects the device where ID[4:0] matches the

DQ[25:21] lines, or it selects all the devices

when DQ[25:21] = 11111.

– Cycle 2: The host ASIC drives the DQ[71:0]

with the data to be written to the data array,

mask array, external SRAM, or register location

of the selected device.

– Cycle 3: Idle cycle. At the termination of this cy-

cle, another operation can begin.

Note: The latency of the SRAM WRITE will be

different than the one described above (see

SRAM PIO Access, page 128).

The burst WRITE operation lasts for n + 2 CLK cy-

cles (where n signifies the number of accesses in

the burst as specified in the BLEN field of the

WBURREG register, please see Figure 21, page

37).

This operation assumes that the host ASIC has

programmed the WBURREG with the starting ad-

dress (ADR) and the length of transfer (BLEN) be-

fore initiating the burst write command (see Table

25, page 38 for format). The sequence is as fol-

lows:

– Cycle 1A: The host ASIC applies the WRITE In-

struction on the CMD[1:0] (CMD[2] = 1), using

CMDV = 1 and the address supplied on the DQ

Bus, as shown in Table 25, page 38. The host

ASIC also supplies the index to the global mask

ray locations in {CMD[10], CMD[5:3]}. The host

ASIC sets ASIC sets CMD[9] to '0' for the nor-

mal WRITE.

– Cycle 1B: The host ASIC continues to apply the

WRITE

Instruction

the

CMD[1:0]

(CMD[2] = 0), using CMDV = 1 and the address

supplied on the DQ Bus. The host ASIC contin-

ues to supply the global mask register index to

mask the WRITE to the data or mask array loca-

tions in {CMD[10], CMD[5:3]}. The host ASIC

selects the device where ID[4:0] matches the

DQ[25:21] lines, or it selects all the devices

when DQ[25:21] = 11111.

DQ[71:26]

DQ[25:21]

DQ[20:19]

DQ[18:7]

DQ[6:0]

Reserved

11: Register

Reserved

DQ[71:26]

DQ[25:21]

DQ[20:19]

DQ[18:16]

DQ[15:0]

Reserved

00: Data Array

Reserved

Do not care. These 16 bits come from the internal

access.

Reserved

01: Mask

Array

Reserved

Do not care. These 16 bits come from the internal

access.

M7040N датащи(PDF) 35 Page - STMicroelectronics

M7040N датащи(HTML) 35 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL