M7040N datasheet(20/159 Pages) STMICROELECTRONICS

20 / 159 page

M7040N

20/159

Command Bus (CMD[10:0]. [1:0] specifies the

command; [10:2] contains the command parame-

ters. The descriptions of individual commands ex-

plains the details of the parameters. The encoding

of commands based on the [1:0] field are:

– 00: PIO READ

– 01: PIO WRITE

– 10: SEARCH

– 11: LEARN

Command Valid (CMDV). Qualifies the CMD bus

as follows:

– 0: No Command

– 1: Command

Address/Data Bus (DQ[71:0]). Carries the Read

and WRITE address as well as the data during

ries the compare data during search operations. It

also carries the SRAM address during SRAM PIO

accesses.

READ Acknowledge (ACK). Indicates that valid

data is available on the DQ Bus during register,

data, and mask array READ operations, or the

data is available on the SRAM data bus during

SRAM READ operations.

Note: ACK Signals require a weak external pull-

down resistor such as 47 or 100 K

Ω.

End of Transfer (EOT). Indicates

the

end

burst transfer during READ or WRITE burst oper-

ations.

Note: EOT Signals require a weak external pull-

down resistor such as 47 K

Ω or 100 KΩ.

SEARCH Successful Flag (SSF). When assert-

ed, this signal indicates that the device is the glo-

bal winner in a SEARCH operation.

SEARCH Successful Flag Valid (SSV). When

asserted, this signal qualifies the SSF signal.

Multiple Hit Flag (MULTI_HIT). When asserted,

this signal indicates that there is more than one lo-

cation having a match on this device.

High Speed (HIGH_SPEED). When this signal is

high, the device will run up to 100MHz and perform

100 million searches per second. However, in this

mode, a TLSZ value of '00' is not supported in a

system of a single device. Furthermore, the device

will only support a TLSZ of '00' and '01' if more

than one device is cascaded to form database ta-

bles.

Clock Tune [3:0] (CLK_TUNE[3:0]). These test

pins should be set to logic level 1001.

SRAM Address (SADR[23:0]). This

bus

con-

tains address lines to access off-chip SRAMs that

contain associative data. See Table 52, page 128

for the details of the generated SRAM address. In

a database of multiple M7040Ns, each corre-

sponding bit of SADR from all cascaded devices

must be connected.

SRAM Chip Enable (CE_L). This is Chip Enable

control for external SRAMs. In a database of mul-

tiple M7040Ns, CE_L of all cascaded devices

must be connected. This signal is then driven by

only one of the devices.

SRAM WriteEnable(WE_L). This is Write En-

able control for external SRAMs. In a database of

multiple M7040Ns, WE_L of all cascaded devices

must be connected together. This signal is then

driven by only one of the devices.

SRAM Output Enable (OE_L). This

Output

Enable control for external SRAMs. Only the last

device drives this signal (with the LRAM bit set).

Address Latch Enable (ALE_L). When this sig-

nal is low, the addresses are valid on the SRAM

Address Bus. In a database of multiple M7040Ns,

the ALE_L of all cascaded devices must be con-

nected. This signal is then driven by only one of

the devices.

Local Hit In (LHI[6:0]). These

pins depth-cas-

cade the device to form a larger table size. One

signal of this bus is connected to the LHO[1] or

LHO[0] of each of the upstream devices in a block.

Connect all unused LHI pins to a logic '0.' (For

information,

see

DEPTH-CASCADING,

page 124.)

Local Hit Out (LHO[1:0]). LHO[1] and

LHO[0]

are the same logical signal. LHO[1] or LHO[0] is

connected to one input of the LHI bus of up to four

downstream devices (in a block that contains up to

eight

devices).

(For

information,

see

DEPTH-CASCADING, page 124.)

Block Hit In (BHI[2:0]). Inputs from the previous

BHO[2:0] are tied to the BHI[2:0] of the current de-

vice (see DEPTH-CASCADING, page 124). In a

four-block system, the last block can contain only

seven devices because the ID code 11111 is used

for broadcast access.

Block Hit Out (BHO[2:0]). These outputs from

the last device in a block are connected to the

BHI[2:0] inputs of the devices in the downstream

blocks (see DEPTH-CASCADING, page 124).

M7040N датащи(PDF) 20 Page - STMicroelectronics

M7040N датащи(HTML) 20 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL