M7040N datasheet(22/159 Pages) STMICROELECTRONICS

22 / 159 page

M7040N

22/159

Figure 12. Clocks for All Timing Diagrams

PLL USAGE

When the device first powers up, it takes 0.5 ms to

lock the internal phase-lock loop (PLL). During this

locking of the PLL, in addition to 32 extra CLK1X

cycles in CLK1X mode and 64 extra cycles in

CLK2X mode, the RST_L must be held low for

proper initialization of the device. Setup and hold

requirements will change in CLK1X mode if the

duty cycle of the CLK1X is varied. All signals into

the device in CLK1X mode are sampled by a clock

that is generated by multiplying CLK1X by two.

Since PLL has a locking range, the device will only

work between the range of frequencies specified

in the timing specification section.

REGISTERS

All registers in the M7040N are 72 bits wide. The

M7040N contains 16 pairs of comparand storage

registers, 16 pairs of global mask registers

(GMRs), eight search successful index registers

and one each of command, information, burst

READ, burst WRITE, and next-free address regis-

ters. Table 9 provides an overview of all the

M7040N registers. The registers are ordered in as-

cending address order. Each register group is then

described in the following subsections.

Table 9. Register Overview

CLK2X

PHS_L

CLK1X

AI04666

(Use for CLK1X MODE)

Address

Abbreviation

Type

Name

0–31

COMP0–31

32 Comparand Registers. Stores comparands from the DQ Bus for

learning later.

32–47, 96–111

MASKS

16 Global Mask Registers Pairs.

48–55

SSR0–7

8 SEARCH Successful Index Registers.

COMMAND

Command Register.

INFO

Information Register.

RBURREG

Burst Read Register.

WBURREG

Burst Write Register.

NFA

Next Free Address Register.

61–63

––

Reserved

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